diff --git a/arch/arm/boot/dts/xilinx/zynq-zed-ad7405.dts b/arch/arm/boot/dts/xilinx/zynq-zed-ad7405.dts
new file mode 100644
index 0000000000000..53943bf0be317
--- /dev/null
+++ b/arch/arm/boot/dts/xilinx/zynq-zed-ad7405.dts
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Analog Devices EVAL-AD7405FMCZ
+ * https://www.analog.com/en/products/ad7405.html
+ *
+ * hdl_project: <ad7405_fmc/zed>
+ * Link: https://github.com/analogdevicesinc/hdl/tree/main/projects/ad7405_fmc
+ *
+ * Copyright (C) 2026 Analog Devices Inc.
+ */
+
+/dts-v1/;
+#include "zynq-zed.dts"
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	vdd1: regulator-vdd1 {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-supply-vdd1";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+	};
+
+	vdd2: regulator-vdd2 {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-supply-vdd2";
+		regulator-min-microvolt = <2500000>;
+		regulator-max-microvolt = <2500000>;
+		regulator-always-on;
+	};
+
+	ad7405 {
+		compatible = "adi,ad7405";
+		clocks = <&axi_clk_gen>;
+		vdd1-supply = <&vdd1>;
+		vdd2-supply = <&vdd2>;
+		io-backends = <&iio_backend>;
+	};
+
+	fpga-axi@0 {
+		compatible = "simple-bus";
+		#address-cells = <0x1>;
+		#size-cells = <0x1>;
+		ranges;
+
+		iio_backend: backend@44a00000 {
+			compatible = "adi,axi-adc-10.0.a";
+			reg = <0x44a00000 0x10000>;
+			#dma-cells = <1>;
+			dmas = <&ad_mc_adc_dma 0>;
+			dma-names = "ad-mc-adc-dma";
+			clocks = <&axi_clk_gen>;
+		};
+
+		ad_mc_adc_dma: dma@44a30000 {
+			compatible = "adi,axi-dmac-1.00.a";
+			reg = <0x44a30000 0x1000>;
+			#dma-cells = <1>;
+			interrupt-parent = <&intc>;
+			interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clkc 15>;
+		};
+
+		axi_clk_gen: axi-clkgen@44a40000 {
+			compatible = "adi,axi-clkgen-2.00.a";
+			reg = <0x44a40000 0x10000>;
+			#clock-cells = <0>;
+			clocks = <&clkc 15>, <&clkc 15>;
+			clock-names = "s_axi_aclk", "clkin1";
+			clock-output-names = "axi_clk_gen";
+
+			assigned-clocks = <&axi_clk_gen>;
+			assigned-clock-rates = <20000000>;
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/xilinx/zynq-zed-adum7701.dts b/arch/arm/boot/dts/xilinx/zynq-zed-adum7701.dts
new file mode 100644
index 0000000000000..f0aaa9c97a6c3
--- /dev/null
+++ b/arch/arm/boot/dts/xilinx/zynq-zed-adum7701.dts
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Analog Devices EV-ADuM7701-8FMCZ
+ * https://www.analog.com/en/products/adum7701.html
+ *
+ * hdl_project: <ad7405_fmc/zed>
+ * Link: https://github.com/analogdevicesinc/hdl/tree/main/projects/ad7405_fmc
+ *
+ * Copyright (C) 2026 Analog Devices Inc.
+ */
+
+/dts-v1/;
+#include "zynq-zed.dts"
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	vdd1: regulator-vdd1 {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-supply-vdd1";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+	};
+
+	vdd2: regulator-vdd2 {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-supply-vdd2";
+		regulator-min-microvolt = <2500000>;
+		regulator-max-microvolt = <2500000>;
+		regulator-always-on;
+	};
+
+	ad7405 {
+		compatible = "adi,adum7701";
+		clocks = <&axi_clk_gen>;
+		vdd1-supply = <&vdd1>;
+		vdd2-supply = <&vdd2>;
+		io-backends = <&iio_backend>;
+	};
+
+	fpga-axi@0 {
+		compatible = "simple-bus";
+		#address-cells = <0x1>;
+		#size-cells = <0x1>;
+		ranges;
+
+		iio_backend: backend@44a00000 {
+			compatible = "adi,axi-adc-10.0.a";
+			reg = <0x44a00000 0x10000>;
+			#dma-cells = <1>;
+			dmas = <&ad_mc_adc_dma 0>;
+			dma-names = "ad-mc-adc-dma";
+			clocks = <&axi_clk_gen>;
+		};
+
+		ad_mc_adc_dma: dma@44a30000 {
+			compatible = "adi,axi-dmac-1.00.a";
+			reg = <0x44a30000 0x1000>;
+			#dma-cells = <1>;
+			interrupt-parent = <&intc>;
+			interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clkc 15>;
+		};
+
+		axi_clk_gen: axi-clkgen@44a40000 {
+			compatible = "adi,axi-clkgen-2.00.a";
+			reg = <0x44a40000 0x10000>;
+			#clock-cells = <0>;
+			clocks = <&clkc 15>, <&clkc 15>;
+			clock-names = "s_axi_aclk", "clkin1";
+			clock-output-names = "axi_clk_gen";
+
+			assigned-clocks = <&axi_clk_gen>;
+			assigned-clock-rates = <21000000>;
+		};
+	};
+};