diff --git a/src/arch/armv8/cache.c b/src/arch/armv8/cache.c
index abdccd3e0..32b77c198 100644
--- a/src/arch/armv8/cache.c
+++ b/src/arch/armv8/cache.c
@@ -114,5 +114,6 @@ void cache_flush_range(vaddr_t base, size_t size)
         cache_addr += min_line_size;
     }
 
-    DMB(ish);
+    /* Ensure the cache maintenance operations complete before returning */
+    DSB(ish);
 }
diff --git a/src/arch/riscv/arch.mk b/src/arch/riscv/arch.mk
index 095f7cbb5..ac25d41a0 100644
--- a/src/arch/riscv/arch.mk
+++ b/src/arch/riscv/arch.mk
@@ -5,12 +5,12 @@ ARCH_SUB?=riscv64
 
 ifeq ($(ARCH_SUB), riscv64)
 CROSS_COMPILE ?= riscv64-unknown-elf-
-riscv_march:=rv64imac_zicsr_zicbom
+riscv_march:=rv64imac_zicsr_zicbom_zifencei
 riscv_mabi:=lp64
 ld_emulation:=elf64lriscv
 else ifeq ($(ARCH_SUB), riscv32)
 CROSS_COMPILE ?= riscv32-unknown-elf-
-riscv_march:=rv32imac_zicsr_zicbom
+riscv_march:=rv32imac_zicsr_zicbom_zifencei
 riscv_mabi:=ilp32
 ld_emulation:=elf32lriscv
 else
diff --git a/src/arch/riscv/relocate.S b/src/arch/riscv/relocate.S
index 2c946578d..b0dfdd156 100644
--- a/src/arch/riscv/relocate.S
+++ b/src/arch/riscv/relocate.S
@@ -53,6 +53,9 @@ switch_space:
     sub a6, a6, a4
     sub a0, a0, a4
 
+    /* Synchronize instruction fetch with the data-side copy of the relocated image */
+    fence.i
+
     /* Update root page table pointer */
     srl a1, a1, PAGE_SHIFT
     li  t0, SATP_MODE_DFLT