diff --git a/doc/PCM-EXPORTER.md b/doc/PCM-EXPORTER.md index c8d4327e..f815f713 100644 --- a/doc/PCM-EXPORTER.md +++ b/doc/PCM-EXPORTER.md @@ -63,7 +63,62 @@ The default output of pcm-sensor-server endpoint in a browser: ![image](https://user-images.githubusercontent.com/25432609/226344012-8783e154-998e-48a7-a2ca-f2c42af9c843.png) +## Security Warning + +pcm-sensor-server collects and serves internal CPU metric information on the system. Do not expose its HTTP/HTTPS endpoints to untrusted or publicly accessible networks. Prefer binding to localhost or a dedicated management interface (see `-l|--listen` above), and use firewalling and/or an authenticated reverse proxy if remote access is required. High request rates can overload the host and lead to a denial of service. + +## Integration with Grafana The PCM exporter can be used together with Grafana to obtain these Intel processor metrics (see [how-to](../scripts/grafana/README.md)): ![pcm grafana output](https://raw.githubusercontent.com/wiki/intel/pcm/pcm-dashboard-full.png) + +# Low-Level Metric Reference + +## Global PCM Events + +| Event Name | Description | +|-----------------------------|-----------------------------------------------------------------------------| +| Measurement_Interval_in_us | How many us elapsed to complete the last measurement | +| Number_of_sockets | Number of CPU sockets in the system | + +## Core Counters per socket + +OS_ID is the OS assigned ID of the logical CPU core and denotes the socket id, core id and thread id. + +The events below are followed by the same {socket="socket id",core="core id",thread="thread id"} as +the OS_ID of their section with source="socket/core/thread" appended that denotes what the quantity +of the event accounts for. + +For example Instructions_Retired_Any{socket="0",core="1",thread="1",source="core"} refers to +Instructions_Retired_Any for socket 0, core 1, thread 1, and accounts for the total instructions +retired of the specified core. + +| Event | Description | +|------------------------------------------------|--------------------------------------------------------------| +| Instructions_Retired_Any | Total number of Retired instructions | +| Clock_Unhalted_Thread | Counts the number of core cycles while the thread is not | +| | in a halt state. | +| Clock_Unhalted_Ref | Counts the number of reference cycles that the thread is | +| | not in a halt state. The thread enters the halt state when | +| | it is running the HLT instruction. This event is not | +| | affected by thread frequency changes but counts as if the | +| | thread is running at the maximum frequency all the time. | +| L3_Cache_Misses | Total number of L3 Cache misses | +| L3_Cache_Hits | Total number of L3 Cache hits | +| L2_Cache_Misses | Total number of L2 Cache misses | +| L2_Cache_Hits | Total number of L2 Cache hits | +| L3_Cache_Occupancy | Computes L3 Cache Occupancy | +| SMI_Count | SMI (System Management Interrupt) count | +| Invariant_TSC | Calculates the invariant TSC clocks (the invariant TSC | +| | means that the TSC continues at a fixed rate regardless of | +| | the C-state or frequency of the processor as long as the | +| | processor remains in the ACPI S0 state. | +| Thermal_Headroom | Celsius degrees before reaching TjMax temperature | +| CStateResidency | This is the percentage of time that the core (or the whole | +| | package) spends in a particular level of C-state | + +References: + +https://software.intel.com/content/www/us/en/develop/articles/intel-performance-counter-monitor.html +https://software.intel.com/content/dam/develop/external/us/en/documents-tps/325384-sdm-vol-3abcd.pdf - Chapter 18 Performance Monitoring diff --git a/doc/PCM-SENSOR-SERVER-README.md b/doc/PCM-SENSOR-SERVER-README.md index 16cbf717..da72de5a 100644 --- a/doc/PCM-SENSOR-SERVER-README.md +++ b/doc/PCM-SENSOR-SERVER-README.md @@ -1,47 +1,3 @@ -# Global PCM Events +# PCM Sensor Server Metric Reference -| Event Name | Description | -|-----------------------------|-----------------------------------------------------------------------------| -| Measurement_Interval_in_us | How many us elapsed to complete the last measurement | -| Number_of_sockets | Number of CPU sockets in the system | - - -# Core Counters per socket - -OS_ID is the OS assigned ID of the logical CPU core and denotes the socket id, core id and thread id. - -The events below are followed by the same {socket="socket id",core="core id",thread="thread id"} as -the OS_ID of their section with source="socket/core/thread" appended that denotes what the quantity -of the event accounts for. - -For example Instructions_Retired_Any{socket="0",core="1",thread="1",source="core"} refers to -Instructions_Retired_Any for socket 0, core 1, thread 1, and accounts for the total instructions -retired of the specified core. - -| Event | Description | -|------------------------------------------------|--------------------------------------------------------------| -| Instructions_Retired_Any | Total number of Retired instructions | -| Clock_Unhalted_Thread | | -| Clock_Unhalted_Ref | Counts the number of reference cycles that the thread is | -| | not in a halt state. The thread enters the halt state when | -| | it is running the HLT instruction. This event is not | -| | affected by thread frequency changes but counts as if the | -| | thread is running at the maximum frequency all the time. | -| L3_Cache_Misses | Total number of L3 Cache misses | -| L3_Cache_Hits | Total number of L3 Cache hits | -| L2_Cache_Misses | Total number of L2 Cache misses | -| L2_Cache_Hits | Total number of L3 Cache hits | -| L3_Cache_Occupancy | Computes L3 Cache Occupancy | -| SMI_Count | SMI (System Management Interrupt) count | -| Invariant_TSC | Calculates the invariant TSC clocks (the invariant TSC | -| | means that the TSC continues at a fixed rate regardless of | -| | the C-state or frequency of the processor as long as the | -| | processor remains in the ACPI S0 state. | -| Thermal_Headroom | Celsius degrees before reaching TjMax temperature | -| CStateResidency | This is the percentage of time that the core (or the whole | -| | package) spends in a particular level of C-state | | - -References: - -https://software.intel.com/content/www/us/en/develop/articles/intel-performance-counter-monitor.html -https://software.intel.com/content/dam/develop/external/us/en/documents-tps/325384-sdm-vol-3abcd.pdf - Chapter 18 Performance Monitoring \ No newline at end of file +The PCM sensor server metric documentation has moved to [PCM-EXPORTER.md](PCM-EXPORTER.md). diff --git a/perfmon b/perfmon index e90417e2..1cc8f8ae 160000 --- a/perfmon +++ b/perfmon @@ -1 +1 @@ -Subproject commit e90417e2e2b3498fee7329050544a78cb2ddb884 +Subproject commit 1cc8f8aee966dbd2938dabb8fe81c747e2d39966