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SystemC#662

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desmonddak wants to merge 31 commits into
intel:mainfrom
desmonddak:systemc
Open

SystemC#662
desmonddak wants to merge 31 commits into
intel:mainfrom
desmonddak:systemc

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@desmonddak
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Description & Motivation

We should have a SystemC translation of our ROHD modules to simulate in a SystemC environment.

Related Issue(s)

None.

Testing

Leverage iverilog tests to drive SystemC testing, except for somethings like lack of 'X' propagation.

Backwards-compatibility

Is this a breaking change that will not be backwards-compatible? If yes, how so?

No.

Documentation

Does the change require any updates to documentation? If so, where? Are they included?

Very basic documentation added to parallel SystemVerilog.

Introduces a singleton service registry (ModuleServices) that provides a
unified query surface for DevTools and inspection tools. Module.build()
now registers the root module with ModuleServices.instance.

Also adds SvService which wraps SystemVerilog synthesis and registers
with ModuleServices for DevTools access to SV metadata.

This is a clean separation: no netlist code is included. The netlist
branch will later extend ModuleServices with a netlistService field.
@desmonddak desmonddak changed the title Systemc SystemC May 9, 2026
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