From f85660c617426391142ce2477257eff0d722dfd1 Mon Sep 17 00:00:00 2001 From: Ceci Herbert Date: Tue, 17 Mar 2026 09:44:09 +0000 Subject: [PATCH] Removed hard coded values for hs-64 voltage They didn't match the ones on its hardware page --- source/Hardware Guide/Headstages/tether-voltage.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/source/Hardware Guide/Headstages/tether-voltage.rst b/source/Hardware Guide/Headstages/tether-voltage.rst index 394479de..66e23ee3 100644 --- a/source/Hardware Guide/Headstages/tether-voltage.rst +++ b/source/Hardware Guide/Headstages/tether-voltage.rst @@ -14,7 +14,7 @@ Setting Headstage Voltage -------------------------- The headstage voltage is set using :ref:`onidatasheet_fmc_link_control` devices on the :ref:`pcie_controller`. Each headstage has a minimum and maximum voltage -requirement (e.g. 5.3 to 5.7 Volts for :ref:`headstage_64`) in order for +requirement listed under the Data Link Serialization/Coaxial Link section on its own hardware page (e.g. :ref:`headstage_64`) in order for circuits on the board to function properly. If the voltage is far too low, the host computer will not be able to detect the headstage. A borderline voltage can still cause connectivity issues as the headstage occasionally dips