diff --git a/DirectProgramming/DPC++FPGA/ReferenceDesigns/gzip/CMakeLists.txt b/DirectProgramming/DPC++FPGA/ReferenceDesigns/gzip/CMakeLists.txt index d738ef43e8..eeb01c63fb 100755 --- a/DirectProgramming/DPC++FPGA/ReferenceDesigns/gzip/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/ReferenceDesigns/gzip/CMakeLists.txt @@ -1,15 +1,14 @@ +# Direct CMake to use icpx rather than the default C++ compiler/linker on Linux +# and icx-cl on Windows if(UNIX) - # Direct CMake to use icpx rather than the default C++ compiler/linker set(CMAKE_CXX_COMPILER icpx) else() # Windows - # Force CMake to use icx-cl rather than the default C++ compiler/linker - # (needed on Windows only) include (CMakeForceCompiler) CMAKE_FORCE_CXX_COMPILER (icx-cl IntelDPCPP) include (Platform/Windows-Clang) endif() -cmake_minimum_required (VERSION 3.4) +cmake_minimum_required (VERSION 3.7.2) project(GZip CXX) @@ -17,4 +16,317 @@ set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}) set(CMAKE_LIBRARY_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}) set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}) -add_subdirectory (src) +############################################################################### +### Customize these build variables +############################################################################### +if(LOW_LATENCY) + # Compile the low latency version of the design + message(STATUS "Compiling the Low Latency variant of the design") + set(SOURCE_FILE src/gzip_ll.cpp src/crc32.cpp src/WriteGzip.cpp src/CompareGzip.cpp src/gzipkernel_ll.cpp ) +else() + # Compile the high bandwidth version of the design + message(STATUS "Compiling the High Bandwidth variation of the design") + set(SOURCE_FILE src/gzip.cpp src/crc32.cpp src/WriteGzip.cpp src/CompareGzip.cpp src/gzipkernel.cpp) +endif() + +set(TARGET_NAME gzip) + +# Use cmake -DFPGA_DEVICE=: to choose a +# different device. Here are a few device examples (this list is not +# exhaustive): +# intel_s10sx_pac:pac_s10 +# intel_s10sx_pac:pac_s10_usm +# intel_a10gx_pac:pac_a10 +# Note that depending on your installation, you may need to specify the full +# path to the board support package (BSP), this usually is in your install +# folder. +# +# You can also specify a device family (E.g. "Arria10" or "Stratix10") or a +# specific part number (E.g. "10AS066N3F40E2SG") to generate a standalone IP. +if(NOT DEFINED FPGA_DEVICE) + set(FPGA_DEVICE "intel_s10sx_pac:pac_s10_usm") +endif() + +# Use cmake -DUSER_FPGA_FLAGS= to set extra flags for FPGA backend +# compilation. +set(USER_FPGA_FLAGS "${USER_FPGA_FLAGS}") + +# Use cmake -DUSER_FLAGS= to set extra flags for general compilation. +set(USER_FLAGS "${USER_FLAGS}") + +# Use cmake -DUSER_INCLUDE_PATHS= to set extra paths for general +# compilation. +set(USER_INCLUDE_PATHS "${USER_INCLUDE_PATHS} ../../include") + +############################################################################### +### no changes after here +############################################################################### + +# Print the device being used for the compiles +message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}") + +# Set design parameters according to the selected chip +if(FPGA_DEVICE MATCHES ".*a10.*") + # A10 parameters + set(NUM_ENGINES 1) + if(DEFINED LOW_LATENCY) + set(SEED "-Xsseed=4") + set(NUM_REORDER "") + else() + set(SEED "-Xsseed=4") + set(NUM_REORDER "") + endif() +elseif(FPGA_DEVICE MATCHES ".*s10.*") + # S10 parameters + set(NUM_ENGINES 2) + if(DEFINED LOW_LATENCY) + set(SEED "-Xsseed=16") + set(NUM_REORDER "") + else() + set(SEED "-Xsseed=4") + # For the High Bandwidth variant, specify 6 reordering units to improve global memory read bandwidth across 4 channels of DDR. + # For Low Latency variant this is not necessary since only one channel of global memory is used (host memory). + set(NUM_REORDER "-Xsnum-reorder=6") + endif() +elseif(FPGA_DEVICE MATCHES ".*agilex.*") + # Agilex™ + set(NUM_ENGINES 2) + if(DEFINED LOW_LATENCY) + set(SEED "-Xsseed=1") + set(NUM_REORDER "") + else() + set(SEED "-Xsseed=8") + # For the High Bandwidth variant, specify 6 reordering units to improve global memory read bandwidth across 4 channels of DDR. + # For Low Latency variant this is not necessary since only one channel of global memory is used (host memory). + set(NUM_REORDER "-Xsnum-reorder=6") + endif() +else() + set(NUM_ENGINES 1) + set(SEED "-Xsseed=1") + set(NUM_REORDER "") +endif() + +if(IGNORE_DEFAULT_SEED) + set(SEED "") +endif() + +# Presence of USM host allocations (and whether to turn on enable the low-latency target) is detected automatically by +# looking at the name of the BSP, or manually by the user when running CMake. +# E.g., cmake .. -DUSER_ENABLE_USM=1 +if(FPGA_DEVICE MATCHES ".*usm.*" OR USER_ENABLE_USM) + set(USM_ENABLED 1) +elseif(LOW_LATENCY) + # Low latency design requires USM, so error out + message(FATAL_ERROR "Error: The Low Latency variant of the design requires USM host allocations") +endif() + + +# Set the names of the makefile targets to be generated by cmake +set(EMULATOR_TARGET fpga_emu) +set(SIMULATOR_TARGET fpga_sim) +set(REPORT_TARGET report) +set(FPGA_TARGET fpga) +set(IP_EXPORT_TARGET fpga_ip_export) + +# Set the names of the generated files per makefile target +set(EMULATOR_OUTPUT_NAME ${TARGET_NAME}.${EMULATOR_TARGET}) +set(SIMULATOR_OUTPUT_NAME ${TARGET_NAME}.${SIMULATOR_TARGET}) +set(REPORT_OUTPUT_NAME ${TARGET_NAME}.${REPORT_TARGET}) +set(FPGA_OUTPUT_NAME ${TARGET_NAME}.${FPGA_TARGET}) + +# Sanitize the include path +set(INCLUDEPATHS_LIST ${USER_INCLUDE_PATHS}) +separate_arguments(INCLUDEPATHS_LIST) +include_directories(${INCLUDEPATHS_LIST}) + +# This is a Windows-specific flag that enables exception handling in host code +if(WIN32) + # add qactypes to link command on Windows only + set(QACTYPES "-Qactypes") + set(WIN_FLAG "/EHsc") +else() + # add qactypes for Linux + set(QACTYPES "-qactypes") +endif() + +set(COMMON_COMPILE_FLAGS -fsycl -fintelfpga -Wall ${WIN_FLAG} ${QACTYPES} ${USER_FLAGS}) +set(COMMON_LINK_FLAGS -fsycl -fintelfpga ${QACTYPES} ${USER_FLAGS}) + +# A SYCL ahead-of-time (AoT) compile processes the device code in two stages. +# 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). +# 2. The "link" stage invokes the compiler's FPGA backend before linking. +# For this reason, FPGA backend flags must be passed as link flags in CMake. +set(EMULATOR_COMPILE_FLAGS -DNUM_ENGINES=${NUM_ENGINES} -DFPGA_EMULATOR) +set(EMULATOR_LINK_FLAGS -DNUM_ENGINES=${NUM_ENGINES}) +set(REPORT_COMPILE_FLAGS -DNUM_ENGINES=${NUM_ENGINES} -DFPGA_HARDWARE) +set(REPORT_LINK_FLAGS ${NUM_REORDER} -Xsopt-arg=\"-nocaching\" -DNUM_ENGINES=${NUM_ENGINES} -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS} -fsycl-link=early) +set(SIMULATOR_COMPILE_FLAGS -DNUM_ENGINES=${NUM_ENGINES} -Xssimulation -DFPGA_SIMULATOR) +set(SIMULATOR_LINK_FLAGS -DNUM_ENGINES=${NUM_ENGINES} -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}) +set(HARDWARE_COMPILE_FLAGS -DNUM_ENGINES=${NUM_ENGINES} -DFPGA_HARDWARE) +set(HARDWARE_LINK_FLAGS ${NUM_REORDER} -Xsparallel=2 ${SEED} -Xsopt-arg=\"-nocaching\" -DNUM_ENGINES=${NUM_ENGINES} -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS} -reuse-exe=${CMAKE_BINARY_DIR}/${FPGA_OUTPUT_NAME}) +# use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA simulator compilation and backend compilation + +# Set the source file names in a string +set(SOURCE_FILE_NAME "${SOURCE_FILE}") + +############################################################################### +### FPGA Emulator +############################################################################### +add_executable(${EMULATOR_TARGET} ${SOURCE_FILE}) +target_compile_options(${EMULATOR_TARGET} PRIVATE ${COMMON_COMPILE_FLAGS}) +target_compile_options(${EMULATOR_TARGET} PRIVATE ${EMULATOR_COMPILE_FLAGS}) +target_link_libraries(${EMULATOR_TARGET} ${COMMON_LINK_FLAGS}) +target_link_libraries(${EMULATOR_TARGET} ${EMULATOR_LINK_FLAGS}) +set_target_properties(${EMULATOR_TARGET} PROPERTIES OUTPUT_NAME ${EMULATOR_OUTPUT_NAME}) + +############################################################################### +### FPGA Simulator +############################################################################### +add_executable(${SIMULATOR_TARGET} ${SOURCE_FILE}) +target_compile_options(${SIMULATOR_TARGET} PRIVATE ${COMMON_COMPILE_FLAGS}) +target_compile_options(${SIMULATOR_TARGET} PRIVATE ${SIMULATOR_COMPILE_FLAGS}) +target_link_libraries(${SIMULATOR_TARGET} ${COMMON_LINK_FLAGS}) +target_link_libraries(${SIMULATOR_TARGET} ${SIMULATOR_LINK_FLAGS}) +set_target_properties(${SIMULATOR_TARGET} PROPERTIES OUTPUT_NAME ${SIMULATOR_OUTPUT_NAME}) + +############################################################################### +### Generate Report +############################################################################### +add_executable(${REPORT_TARGET} ${SOURCE_FILE}) +target_compile_options(${REPORT_TARGET} PRIVATE ${COMMON_COMPILE_FLAGS}) +target_compile_options(${REPORT_TARGET} PRIVATE ${REPORT_COMPILE_FLAGS}) + +# The report target does not need the QACTYPES flag at link stage +set(MODIFIED_COMMON_LINK_FLAGS_REPORT ${COMMON_LINK_FLAGS}) +list(REMOVE_ITEM MODIFIED_COMMON_LINK_FLAGS_REPORT ${QACTYPES}) + +target_link_libraries(${REPORT_TARGET} ${MODIFIED_COMMON_LINK_FLAGS_REPORT}) +target_link_libraries(${REPORT_TARGET} ${REPORT_LINK_FLAGS}) +set_target_properties(${REPORT_TARGET} PROPERTIES OUTPUT_NAME ${REPORT_OUTPUT_NAME}) + +############################################################################### +### FPGA Hardware +############################################################################### +add_executable(${FPGA_TARGET} EXCLUDE_FROM_ALL ${SOURCE_FILE}) +target_compile_options(${FPGA_TARGET} PRIVATE ${COMMON_COMPILE_FLAGS}) +target_compile_options(${FPGA_TARGET} PRIVATE ${HARDWARE_COMPILE_FLAGS}) +target_link_libraries(${FPGA_TARGET} ${COMMON_LINK_FLAGS}) +target_link_libraries(${FPGA_TARGET} ${HARDWARE_LINK_FLAGS}) +set_target_properties(${FPGA_TARGET} PROPERTIES OUTPUT_NAME ${FPGA_OUTPUT_NAME}) + +############################################################################### +### This part only manipulates cmake variables to print the commands to the user +############################################################################### + +# set the correct object file extension depending on the target platform +if(WIN32) + set(OBJ_EXTENSION "obj") +else() + set(OBJ_EXTENSION "o") +endif() + + +function(getCompileCommands includes common_compile_flags special_compile_flags common_link_flags special_link_flags target output_name) + + set(file_names ${SOURCE_FILE_NAME}) + foreach(source ${file_names}) + # Get the relative path to the source and object files + file(RELATIVE_PATH CURRENT_SOURCE_FILE ${CMAKE_CURRENT_BINARY_DIR} ${CMAKE_CURRENT_LIST_DIR}/${source}) + file(RELATIVE_PATH OBJ_FILE ${CMAKE_CURRENT_BINARY_DIR} ${CMAKE_CURRENT_BINARY_DIR}/CMakeFiles/${EMULATOR_TARGET}.dir/${source}.${OBJ_EXTENSION}) + + # Creating a string that contains the compile command + # Start by the compiler invocation + set(COMPILE_COMMAND "${COMPILE_COMMAND}${CMAKE_CXX_COMPILER}") + + # Add all the potential includes + foreach(INCLUDE ${includes}) + file(RELATIVE_PATH INCLUDE ${CMAKE_CURRENT_BINARY_DIR} ${CMAKE_CURRENT_LIST_DIR}/${INCLUDE}) + set(COMPILE_COMMAND "${COMPILE_COMMAND} -I${INCLUDE}") + endforeach() + + # Add all the common compile flags + foreach(FLAG ${common_compile_flags}) + set(COMPILE_COMMAND "${COMPILE_COMMAND} ${FLAG}") + endforeach() + + # Add all the specific compile flags + foreach(FLAG ${special_compile_flags}) + set(COMPILE_COMMAND "${COMPILE_COMMAND} ${FLAG}") + endforeach() + + # Get the location of the object file + file(RELATIVE_PATH OBJ_FILE ${CMAKE_CURRENT_BINARY_DIR} ${CMAKE_CURRENT_BINARY_DIR}/CMakeFiles/${target}.dir/${source}.${OBJ_EXTENSION}) + + # Add the source file and the output file + set(COMPILE_COMMAND "${COMPILE_COMMAND} -c ${CURRENT_SOURCE_FILE} -o ${OBJ_FILE}\n") + endforeach() + + set(COMPILE_COMMAND "${COMPILE_COMMAND}" PARENT_SCOPE) + + # Creating a string that contains the link command + # Start by the compiler invocation + set(LINK_COMMAND "${LINK_COMMAND}${CMAKE_CXX_COMPILER}") + + # Add all the common link flags + foreach(FLAG ${common_link_flags}) + set(LINK_COMMAND "${LINK_COMMAND} ${FLAG}") + endforeach() + + # Add all the specific link flags + foreach(FLAG ${special_link_flags}) + set(LINK_COMMAND "${LINK_COMMAND} ${FLAG}") + endforeach() + + # Add the output file + set(LINK_COMMAND "${LINK_COMMAND} -o ${output_name}") + + foreach(source ${file_names}) + # Get the relative path to the source and object files + file(RELATIVE_PATH OBJ_FILE ${CMAKE_CURRENT_BINARY_DIR} ${CMAKE_CURRENT_BINARY_DIR}/CMakeFiles/${EMULATOR_TARGET}.dir/${source}.${OBJ_EXTENSION}) + + # Add the source file and the output file + set(LINK_COMMAND "${LINK_COMMAND} ${OBJ_FILE}") + endforeach() + + set(LINK_COMMAND "${LINK_COMMAND}" PARENT_SCOPE) + + +endfunction() + +# Windows executable is going to have the .exe extension +if(WIN32) + set(EXECUTABLE_EXTENSION ".exe") +endif() + +# Display the compile instructions in the emulation flow +getCompileCommands("${INCLUDEPATHS_LIST}" "${COMMON_COMPILE_FLAGS}" "${EMULATOR_COMPILE_FLAGS}" "${COMMON_LINK_FLAGS}" "${EMULATOR_LINK_FLAGS}" "${EMULATOR_TARGET}" "${EMULATOR_OUTPUT_NAME}${EXECUTABLE_EXTENSION}") + + +add_custom_target( displayEmulationCompileCommands ALL + ${CMAKE_COMMAND} -E cmake_echo_color --cyan "" + COMMENT "To compile manually:\n${COMPILE_COMMAND}\nTo link manually:\n${LINK_COMMAND}") +add_dependencies(${EMULATOR_TARGET} displayEmulationCompileCommands) + +# Display the compile instructions in the simulation flow +getCompileCommands("${INCLUDEPATHS_LIST}" "${COMMON_COMPILE_FLAGS}" "${SIMULATOR_COMPILE_FLAGS}" "${COMMON_LINK_FLAGS}" "${SIMULATOR_LINK_FLAGS}" "${SIMULATOR_TARGET}" "${SIMULATOR_OUTPUT_NAME}${EXECUTABLE_EXTENSION}") + +add_custom_target( displaySimulationCompileCommands ALL + ${CMAKE_COMMAND} -E cmake_echo_color --cyan "" + COMMENT "To compile manually:\n${COMPILE_COMMAND}\nTo link manually:\n${LINK_COMMAND}") +add_dependencies(${SIMULATOR_TARGET} displaySimulationCompileCommands) + +# Display the compile instructions in the report flow +getCompileCommands("${INCLUDEPATHS_LIST}" "${COMMON_COMPILE_FLAGS}" "${REPORT_COMPILE_FLAGS}" "${MODIFIED_COMMON_LINK_FLAGS_REPORT}" "${REPORT_LINK_FLAGS}" "${REPORT_TARGET}" "${REPORT_OUTPUT_NAME}${EXECUTABLE_EXTENSION}") + +add_custom_target( displayReportCompileCommands ALL + ${CMAKE_COMMAND} -E cmake_echo_color --cyan "" + COMMENT "To compile manually:\n${COMPILE_COMMAND}\nTo link manually:\n${LINK_COMMAND}") +add_dependencies(${REPORT_TARGET} displayReportCompileCommands) + +# Display the compile instructions in the fpga flow +getCompileCommands("${INCLUDEPATHS_LIST}" "${COMMON_COMPILE_FLAGS}" "${FPGA_COMPILE_FLAGS}" "${COMMON_LINK_FLAGS}" "${FPGA_LINK_FLAGS}" "${FPGA_TARGET}" "${FPGA_OUTPUT_NAME}${EXECUTABLE_EXTENSION}") + +add_custom_target( displayFPGACompileCommands ALL + ${CMAKE_COMMAND} -E cmake_echo_color --cyan "" + COMMENT "To compile manually:\n${COMPILE_COMMAND}\nTo link manually:\n${LINK_COMMAND}") +add_dependencies(${FPGA_TARGET} displayFPGACompileCommands) \ No newline at end of file diff --git a/DirectProgramming/DPC++FPGA/ReferenceDesigns/gzip/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/ReferenceDesigns/gzip/src/CMakeLists.txt index aa37c8f46d..e69de29bb2 100755 --- a/DirectProgramming/DPC++FPGA/ReferenceDesigns/gzip/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/ReferenceDesigns/gzip/src/CMakeLists.txt @@ -1,151 +0,0 @@ -set(TARGET_NAME gzip) - - -if(LOW_LATENCY) - # Compile the low latency version of the design - message(STATUS "Compiling the Low Latency variant of the design") - set(SOURCE_FILE gzip_ll.cpp crc32.cpp WriteGzip.cpp CompareGzip.cpp) - set(DEVICE_SOURCE_FILE gzipkernel_ll.cpp) - set(DEVICE_HEADER_FILE gzipkernel_ll.hpp) -else() - # Compile the high bandwidth version of the design - message(STATUS "Compiling the High Bandwidth variation of the design") - set(SOURCE_FILE gzip.cpp crc32.cpp WriteGzip.cpp CompareGzip.cpp) - set(DEVICE_SOURCE_FILE gzipkernel.cpp) - set(DEVICE_HEADER_FILE gzipkernel.hpp) -endif() - -set(EMULATOR_TARGET ${TARGET_NAME}.fpga_emu) -set(SIMULATOR_TARGET ${TARGET_NAME}.fpga_sim) -set(FPGA_TARGET ${TARGET_NAME}.fpga) - -# FPGA board selection -if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE "intel_a10gx_pac:pac_a10") - message(STATUS "FPGA_DEVICE was not specified.\ - \nConfiguring the design to run on the default FPGA board ${FPGA_DEVICE} (Intel(R) PAC with Intel Arria(R) 10 GX FPGA). \ - \nPlease refer to the README for information on board selection.") -else() - message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}") -endif() - -# This is a Windows-specific flag that enables error handling in host code -if(WIN32) - set(WIN_FLAG "/EHsc") -endif() - -# Set design parameters according to the selected chip -if(FPGA_DEVICE MATCHES ".*a10.*") - # A10 parameters - set(NUM_ENGINES 1) - if(DEFINED LOW_LATENCY) - set(SEED "-Xsseed=4") - set(NUM_REORDER "") - else() - set(SEED "-Xsseed=4") - set(NUM_REORDER "") - endif() -elseif(FPGA_DEVICE MATCHES ".*s10.*") - # S10 parameters - set(NUM_ENGINES 2) - if(DEFINED LOW_LATENCY) - set(SEED "-Xsseed=16") - set(NUM_REORDER "") - else() - set(SEED "-Xsseed=4") - # For the High Bandwidth variant, specify 6 reordering units to improve global memory read bandwidth across 4 channels of DDR. - # For Low Latency variant this is not necessary since only one channel of global memory is used (host memory). - set(NUM_REORDER "-Xsnum-reorder=6") - endif() -elseif(FPGA_DEVICE MATCHES ".*agilex.*") - # Agilex™ - set(NUM_ENGINES 2) - if(DEFINED LOW_LATENCY) - set(SEED "-Xsseed=1") - set(NUM_REORDER "") - else() - set(SEED "-Xsseed=8") - # For the High Bandwidth variant, specify 6 reordering units to improve global memory read bandwidth across 4 channels of DDR. - # For Low Latency variant this is not necessary since only one channel of global memory is used (host memory). - set(NUM_REORDER "-Xsnum-reorder=6") - endif() -else() - set(NUM_ENGINES 1) - set(SEED "-Xsseed=1") - set(NUM_REORDER "") -endif() - -if(IGNORE_DEFAULT_SEED) - set(SEED "") -endif() - - -# Presence of USM host allocations (and whether to turn on enable the low-latency target) is detected automatically by -# looking at the name of the BSP, or manually by the user when running CMake. -# E.g., cmake .. -DUSER_ENABLE_USM=1 -if(FPGA_DEVICE MATCHES ".*usm.*" OR USER_ENABLE_USM) - set(USM_ENABLED 1) -elseif(LOW_LATENCY) - # Low latency design requires USM, so error out - message(FATAL_ERROR "Error: The Low Latency variant of the design requires USM host allocations") -endif() - -message(STATUS "NUM_ENGINES=${NUM_ENGINES}") -message(STATUS "SEED=${SEED}") -message(STATUS "NUM_REORDER=${NUM_REORDER}") - -# A SYCL ahead-of-time (AoT) compile processes the device code in two stages. -# 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). -# 2. The "link" stage invokes the compiler's FPGA backend before linking. -# For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -DNUM_ENGINES=${NUM_ENGINES} -DFPGA_EMULATOR") -set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga -DNUM_ENGINES=${NUM_ENGINES}") -set(SIMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -Xssimulation -DNUM_ENGINES=${NUM_ENGINES} -DFPGA_SIMULATOR") -set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xstarget=${FPGA_DEVICE} -DNUM_ENGINES=${NUM_ENGINES} ${USER_SIMULATOR_FLAGS}") -set(HARDWARE_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -DNUM_ENGINES=${NUM_ENGINES}") -set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xsparallel=2 -Xsopt-arg=\"-nocaching\" -Xstarget=${FPGA_DEVICE} -DNUM_ENGINES=${NUM_ENGINES} ${USER_HARDWARE_FLAGS}") -# use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA backend compilation - -############################################################################### -### FPGA Emulator -############################################################################### -add_executable(${EMULATOR_TARGET} ${SOURCE_FILE} ${DEVICE_SOURCE_FILE}) -target_include_directories(${EMULATOR_TARGET} PRIVATE ../../../include) -set_target_properties(${EMULATOR_TARGET} PROPERTIES COMPILE_FLAGS "${EMULATOR_COMPILE_FLAGS}") -set_target_properties(${EMULATOR_TARGET} PROPERTIES LINK_FLAGS "${EMULATOR_LINK_FLAGS}") -add_custom_target(fpga_emu DEPENDS ${EMULATOR_TARGET}) - -############################################################################### -### FPGA Simulator -############################################################################### -add_executable(${SIMULATOR_TARGET} ${SOURCE_FILE} ${DEVICE_SOURCE_FILE}) -target_include_directories(${SIMULATOR_TARGET} PRIVATE ../../../include) -set_target_properties(${SIMULATOR_TARGET} PROPERTIES COMPILE_FLAGS "${SIMULATOR_COMPILE_FLAGS}") -set_target_properties(${SIMULATOR_TARGET} PROPERTIES LINK_FLAGS "${SIMULATOR_LINK_FLAGS}") -add_custom_target(fpga_sim DEPENDS ${SIMULATOR_TARGET}) - -############################################################################### -### Generate Report -############################################################################### -set(FPGA_EARLY_IMAGE ${TARGET_NAME}_report.a) -# The compile output is not an executable, but an intermediate compilation result unique to SYCL. -add_executable(${FPGA_EARLY_IMAGE} ${SOURCE_FILE} ${DEVICE_SOURCE_FILE}) -target_include_directories(${FPGA_EARLY_IMAGE} PRIVATE ../../../include) -add_custom_target(report DEPENDS ${FPGA_EARLY_IMAGE}) -set_target_properties(${FPGA_EARLY_IMAGE} PROPERTIES COMPILE_FLAGS "${HARDWARE_COMPILE_FLAGS}") -set_target_properties(${FPGA_EARLY_IMAGE} PROPERTIES LINK_FLAGS "${HARDWARE_LINK_FLAGS} ${NUM_REORDER} ${SEED} -fsycl-link=early") -# fsycl-link=early stops the compiler after RTL generation, before invoking Quartus - -############################################################################### -### FPGA Hardware -############################################################################### -add_executable(${FPGA_TARGET} EXCLUDE_FROM_ALL ${SOURCE_FILE} ${DEVICE_SOURCE_FILE}) -target_include_directories(${FPGA_TARGET} PRIVATE ../../../include) -add_custom_target(fpga DEPENDS ${FPGA_TARGET}) -set_target_properties(${FPGA_TARGET} PROPERTIES COMPILE_FLAGS "${HARDWARE_COMPILE_FLAGS}") -set_target_properties(${FPGA_TARGET} PROPERTIES LINK_FLAGS "${HARDWARE_LINK_FLAGS} ${NUM_REORDER} ${SEED} -reuse-exe=${CMAKE_BINARY_DIR}/${FPGA_TARGET}") -# The -reuse-exe flag enables rapid recompilation of host-only code changes. -# See DPC++FPGA/GettingStarted/fast_recompile for details. - - - diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Features/loop_unroll/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/Features/loop_unroll/CMakeLists.txt index f063870e70..2fb52edd11 100755 --- a/DirectProgramming/DPC++FPGA/Tutorials/Features/loop_unroll/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/Tutorials/Features/loop_unroll/CMakeLists.txt @@ -1,15 +1,14 @@ +# Direct CMake to use icpx rather than the default C++ compiler/linker on Linux +# and icx-cl on Windows if(UNIX) - # Direct CMake to use icpx rather than the default C++ compiler/linker set(CMAKE_CXX_COMPILER icpx) else() # Windows - # Force CMake to use icx-cl rather than the default C++ compiler/linker - # (needed on Windows only) include (CMakeForceCompiler) CMAKE_FORCE_CXX_COMPILER (icx-cl IntelDPCPP) include (Platform/Windows-Clang) endif() -cmake_minimum_required (VERSION 3.4) +cmake_minimum_required (VERSION 3.7.2) project(LoopUnroll CXX) @@ -17,4 +16,285 @@ set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}) set(CMAKE_LIBRARY_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}) set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}) -add_subdirectory (src) +############################################################################### +### Customize these build variables +############################################################################### +set(SOURCE_FILES src/loop_unroll.cpp) +set(TARGET_NAME loop_unroll) + +# Use cmake -DFPGA_DEVICE=: to choose a +# different device. Here are a few device examples (this list is not +# exhaustive): +# intel_s10sx_pac:pac_s10 +# intel_s10sx_pac:pac_s10_usm +# intel_a10gx_pac:pac_a10 +# Note that depending on your installation, you may need to specify the full +# path to the board support package (BSP), this usually is in your install +# folder. +# +# You can also specify a device family (E.g. "Arria10" or "Stratix10") or a +# specific part number (E.g. "10AS066N3F40E2SG") to generate a standalone IP. +if(NOT DEFINED FPGA_DEVICE) + set(FPGA_DEVICE "intel_s10sx_pac:pac_s10_usm") +endif() + +# Use cmake -DUSER_FPGA_FLAGS= to set extra flags for FPGA backend +# compilation. +set(USER_FPGA_FLAGS ${USER_FPGA_FLAGS}) + +# Use cmake -DUSER_FLAGS= to set extra flags for general compilation. +set(USER_FLAGS ${USER_FLAGS}) + +# Use cmake -DUSER_INCLUDE_PATHS= to set extra paths for general +# compilation. +set(USER_INCLUDE_PATHS ${USER_INCLUDE_PATHS} ../../../include) + +# Use cmake -DUSER_LIB_PATHS= to set extra paths to target_link_libraries +set(USER_LIB_PATHS ${USER_LIB_PATHS}) + +# Use cmake -DUSER_LIBS= to add extra static libraries +set(USER_LIBS ${USER_LIBS}) + +############################################################################### +### no changes after here +############################################################################### + +# Print the device being used for the compiles +message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}") + +# Set the names of the makefile targets to be generated by cmake +set(EMULATOR_TARGET fpga_emu) +set(SIMULATOR_TARGET fpga_sim) +set(REPORT_TARGET report) +set(FPGA_TARGET fpga) +set(IP_EXPORT_TARGET fpga_ip_export) + +# Set the names of the generated files per makefile target +set(EMULATOR_OUTPUT_NAME ${TARGET_NAME}.${EMULATOR_TARGET}) +set(SIMULATOR_OUTPUT_NAME ${TARGET_NAME}.${SIMULATOR_TARGET}) +set(REPORT_OUTPUT_NAME ${TARGET_NAME}.${REPORT_TARGET}) +set(FPGA_OUTPUT_NAME ${TARGET_NAME}.${FPGA_TARGET}) + +message(STATUS "Additional USER_FPGA_FLAGS=${USER_FPGA_FLAGS}") +message(STATUS "Additional USER_FLAGS=${USER_FLAGS}") + +include_directories(${USER_INCLUDE_PATHS}) +message(STATUS "Additional USER_INCLUDE_PATHS=${USER_INCLUDE_PATHS}") + +link_directories(${USER_LIB_PATHS}) +message(STATUS "Additional USER_LIB_PATHS=${USER_LIB_PATHS}") + +link_libraries(${USER_LIBS}) +message(STATUS "Additional USER_LIBS=${USER_LIBS}") + +# This is a Windows-specific flag that enables exception handling in host code +if(WIN32) + # add qactypes to link command on Windows only + set(QACTYPES "-Qactypes") + set(WIN_FLAG "/EHsc") +else() + # add qactypes for Linux + set(QACTYPES "-qactypes") +endif() + +set(COMMON_COMPILE_FLAGS -fsycl -fintelfpga -Wall ${WIN_FLAG} ${QACTYPES} ${USER_FLAGS}) +set(COMMON_LINK_FLAGS -fsycl -fintelfpga ${QACTYPES} ${USER_FLAGS}) + +# A SYCL ahead-of-time (AoT) compile processes the device code in two stages. +# 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). +# 2. The "link" stage invokes the compiler's FPGA backend before linking. +# For this reason, FPGA backend flags must be passed as link flags in CMake. +set(EMULATOR_COMPILE_FLAGS -DFPGA_EMULATOR) +set(EMULATOR_LINK_FLAGS ) +set(REPORT_COMPILE_FLAGS -DFPGA_HARDWARE) +set(REPORT_LINK_FLAGS -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_FPGA_FLAGS} -fsycl-link=early) +set(SIMULATOR_COMPILE_FLAGS -Xssimulation -DFPGA_SIMULATOR) +set(SIMULATOR_LINK_FLAGS -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} ${USER_FPGA_FLAGS} -reuse-exe=${CMAKE_BINARY_DIR}/${SIMULATOR_OUTPUT_NAME}) +set(HARDWARE_COMPILE_FLAGS -DFPGA_HARDWARE) +set(HARDWARE_LINK_FLAGS -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_FPGA_FLAGS} -reuse-exe=${CMAKE_BINARY_DIR}/${FPGA_OUTPUT_NAME}) + +# Set the source file names in a string +set(SOURCE_FILE_NAME "${SOURCE_FILES}") + +############################################################################### +### FPGA Emulator +############################################################################### +add_executable(${EMULATOR_TARGET} ${SOURCE_FILES}) +target_compile_options(${EMULATOR_TARGET} PRIVATE ${COMMON_COMPILE_FLAGS}) +target_compile_options(${EMULATOR_TARGET} PRIVATE ${EMULATOR_COMPILE_FLAGS}) +target_link_libraries(${EMULATOR_TARGET} ${COMMON_LINK_FLAGS}) +target_link_libraries(${EMULATOR_TARGET} ${EMULATOR_LINK_FLAGS}) +set_target_properties(${EMULATOR_TARGET} PROPERTIES OUTPUT_NAME ${EMULATOR_OUTPUT_NAME}) + +############################################################################### +### FPGA Simulator +############################################################################### +add_executable(${SIMULATOR_TARGET} ${SOURCE_FILES}) +target_compile_options(${SIMULATOR_TARGET} PRIVATE ${COMMON_COMPILE_FLAGS}) +target_compile_options(${SIMULATOR_TARGET} PRIVATE ${SIMULATOR_COMPILE_FLAGS}) +target_link_libraries(${SIMULATOR_TARGET} ${COMMON_LINK_FLAGS}) +target_link_libraries(${SIMULATOR_TARGET} ${SIMULATOR_LINK_FLAGS}) +set_target_properties(${SIMULATOR_TARGET} PROPERTIES OUTPUT_NAME ${SIMULATOR_OUTPUT_NAME}) + +############################################################################### +### Generate Report +############################################################################### +add_executable(${REPORT_TARGET} ${SOURCE_FILES}) +target_compile_options(${REPORT_TARGET} PRIVATE ${COMMON_COMPILE_FLAGS}) +target_compile_options(${REPORT_TARGET} PRIVATE ${REPORT_COMPILE_FLAGS}) + +# The report target does not need the QACTYPES flag at link stage +set(MODIFIED_COMMON_LINK_FLAGS_REPORT ${COMMON_LINK_FLAGS}) +list(REMOVE_ITEM MODIFIED_COMMON_LINK_FLAGS_REPORT ${QACTYPES}) + +target_link_libraries(${REPORT_TARGET} ${MODIFIED_COMMON_LINK_FLAGS_REPORT}) +target_link_libraries(${REPORT_TARGET} ${REPORT_LINK_FLAGS}) +set_target_properties(${REPORT_TARGET} PROPERTIES OUTPUT_NAME ${REPORT_OUTPUT_NAME}) + +############################################################################### +### FPGA Hardware +############################################################################### +add_executable(${FPGA_TARGET} EXCLUDE_FROM_ALL ${SOURCE_FILES}) +target_compile_options(${FPGA_TARGET} PRIVATE ${COMMON_COMPILE_FLAGS}) +target_compile_options(${FPGA_TARGET} PRIVATE ${HARDWARE_COMPILE_FLAGS}) +target_link_libraries(${FPGA_TARGET} ${COMMON_LINK_FLAGS}) +target_link_libraries(${FPGA_TARGET} ${HARDWARE_LINK_FLAGS}) +set_target_properties(${FPGA_TARGET} PROPERTIES OUTPUT_NAME ${FPGA_OUTPUT_NAME}) + +############################################################################### +### This part only manipulates cmake variables to print the commands to the user +############################################################################### + +# set the correct object file extension depending on the target platform +if(WIN32) + set(OBJ_EXTENSION "obj") +else() + set(OBJ_EXTENSION "o") +endif() + + +function(getCompileCommands common_compile_flags special_compile_flags common_link_flags special_link_flags target output_name) + + set(file_names ${SOURCE_FILE_NAME}) + set(COMPILE_COMMAND ) + set(LINK_COMMAND ) + + foreach(source ${file_names}) + # Get the relative path to the source and object files + file(RELATIVE_PATH CURRENT_SOURCE_FILE ${CMAKE_CURRENT_BINARY_DIR} ${CMAKE_CURRENT_LIST_DIR}/${source}) + file(RELATIVE_PATH OBJ_FILE ${CMAKE_CURRENT_BINARY_DIR} ${CMAKE_CURRENT_BINARY_DIR}/CMakeFiles/${target}.dir/${source}.${OBJ_EXTENSION}) + + # Creating a string that contains the compile command + # Start by the compiler invocation + set(COMPILE_COMMAND "${COMPILE_COMMAND}${CMAKE_CXX_COMPILER}") + + # Add all the potential includes + foreach(INCLUDE ${USER_INCLUDE_PATHS}) + if(NOT IS_ABSOLUTE ${INCLUDE}) + file(RELATIVE_PATH INCLUDE ${CMAKE_CURRENT_BINARY_DIR} ${CMAKE_CURRENT_LIST_DIR}/${INCLUDE}) + endif() + set(COMPILE_COMMAND "${COMPILE_COMMAND} -I${INCLUDE}") + endforeach() + + # Add all the common compile flags + foreach(FLAG ${common_compile_flags}) + set(COMPILE_COMMAND "${COMPILE_COMMAND} ${FLAG}") + endforeach() + + # Add all the specific compile flags + foreach(FLAG ${special_compile_flags}) + set(COMPILE_COMMAND "${COMPILE_COMMAND} ${FLAG}") + endforeach() + + # Get the location of the object file + file(RELATIVE_PATH OBJ_FILE ${CMAKE_CURRENT_BINARY_DIR} ${CMAKE_CURRENT_BINARY_DIR}/CMakeFiles/${target}.dir/${source}.${OBJ_EXTENSION}) + + # Add the source file and the output file + set(COMPILE_COMMAND "${COMPILE_COMMAND} -c ${CURRENT_SOURCE_FILE} -o ${OBJ_FILE}\n") + endforeach() + + set(COMPILE_COMMAND "${COMPILE_COMMAND}" PARENT_SCOPE) + + # Creating a string that contains the link command + # Start by the compiler invocation + set(LINK_COMMAND "${LINK_COMMAND}${CMAKE_CXX_COMPILER}") + + # Add all the common link flags + foreach(FLAG ${common_link_flags}) + set(LINK_COMMAND "${LINK_COMMAND} ${FLAG}") + endforeach() + + # Add all the specific link flags + foreach(FLAG ${special_link_flags}) + set(LINK_COMMAND "${LINK_COMMAND} ${FLAG}") + endforeach() + + # Add the output file + set(LINK_COMMAND "${LINK_COMMAND} -o ${output_name}") + + foreach(source ${file_names}) + # Get the relative path to the source and object files + file(RELATIVE_PATH OBJ_FILE ${CMAKE_CURRENT_BINARY_DIR} ${CMAKE_CURRENT_BINARY_DIR}/CMakeFiles/${EMULATOR_TARGET}.dir/${source}.${OBJ_EXTENSION}) + + # Add the source file and the output file + set(LINK_COMMAND "${LINK_COMMAND} ${OBJ_FILE}") + endforeach() + + # Add all the potential library paths + foreach(LIB_PATH ${USER_LIB_PATHS}) + if(NOT IS_ABSOLUTE ${LIB_PATH}) + file(RELATIVE_PATH LIB_PATH ${CMAKE_CURRENT_BINARY_DIR} ${CMAKE_CURRENT_LIST_DIR}/${LIB_PATH}) + endif() + if(NOT WIN32) + set(LINK_COMMAND "${LINK_COMMAND} -L${LIB_PATH}") + else() + set(LINK_COMMAND "${LINK_COMMAND} -L${LIB_PATH} -Wl,-rpath,${LIB_PATH}") + endif() + endforeach() + + # Add all the potential includes + foreach(LIB ${USER_LIBS}) + set(LINK_COMMAND "${LINK_COMMAND} -l${LIB}") + endforeach() + + set(LINK_COMMAND "${LINK_COMMAND}" PARENT_SCOPE) + +endfunction() + +# Windows executable is going to have the .exe extension +if(WIN32) + set(EXECUTABLE_EXTENSION ".exe") +endif() + +# Display the compile instructions in the emulation flow +getCompileCommands("${COMMON_COMPILE_FLAGS}" "${EMULATOR_COMPILE_FLAGS}" "${COMMON_LINK_FLAGS}" "${EMULATOR_LINK_FLAGS}" "${EMULATOR_TARGET}" "${EMULATOR_OUTPUT_NAME}${EXECUTABLE_EXTENSION}") + + +add_custom_target( displayEmulationCompileCommands ALL + ${CMAKE_COMMAND} -E cmake_echo_color --cyan "" + COMMENT "To compile manually:\n${COMPILE_COMMAND}\nTo link manually:\n${LINK_COMMAND}") +add_dependencies(${EMULATOR_TARGET} displayEmulationCompileCommands) + +# Display the compile instructions in the simulation flow +getCompileCommands("${COMMON_COMPILE_FLAGS}" "${SIMULATOR_COMPILE_FLAGS}" "${COMMON_LINK_FLAGS}" "${SIMULATOR_LINK_FLAGS}" "${SIMULATOR_TARGET}" "${SIMULATOR_OUTPUT_NAME}${EXECUTABLE_EXTENSION}") + +add_custom_target( displaySimulationCompileCommands ALL + ${CMAKE_COMMAND} -E cmake_echo_color --cyan "" + COMMENT "To compile manually:\n${COMPILE_COMMAND}\nTo link manually:\n${LINK_COMMAND}") +add_dependencies(${SIMULATOR_TARGET} displaySimulationCompileCommands) + +# Display the compile instructions in the report flow +getCompileCommands("${COMMON_COMPILE_FLAGS}" "${REPORT_COMPILE_FLAGS}" "${MODIFIED_COMMON_LINK_FLAGS_REPORT}" "${REPORT_LINK_FLAGS}" "${REPORT_TARGET}" "${REPORT_OUTPUT_NAME}${EXECUTABLE_EXTENSION}") + +add_custom_target( displayReportCompileCommands ALL + ${CMAKE_COMMAND} -E cmake_echo_color --cyan "" + COMMENT "To compile manually:\n${COMPILE_COMMAND}\nTo link manually:\n${LINK_COMMAND}") +add_dependencies(${REPORT_TARGET} displayReportCompileCommands) + +# Display the compile instructions in the fpga flow +getCompileCommands("${COMMON_COMPILE_FLAGS}" "${HARDWARE_COMPILE_FLAGS}" "${COMMON_LINK_FLAGS}" "${HARDWARE_LINK_FLAGS}" "${FPGA_TARGET}" "${FPGA_OUTPUT_NAME}${EXECUTABLE_EXTENSION}") + +add_custom_target( displayFPGACompileCommands ALL + ${CMAKE_COMMAND} -E cmake_echo_color --cyan "" + COMMENT "To compile manually:\n${COMPILE_COMMAND}\nTo link manually:\n${LINK_COMMAND}") +add_dependencies(${FPGA_TARGET} displayFPGACompileCommands) diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Features/loop_unroll/README.md b/DirectProgramming/DPC++FPGA/Tutorials/Features/loop_unroll/README.md index 6c9c494a0a..b25a8d781d 100755 --- a/DirectProgramming/DPC++FPGA/Tutorials/Features/loop_unroll/README.md +++ b/DirectProgramming/DPC++FPGA/Tutorials/Features/loop_unroll/README.md @@ -125,95 +125,75 @@ The basic steps to build and run a sample using VS Code include: To learn more about the extensions and how to configure the oneAPI environment, see the [Using Visual Studio Code with Intel® oneAPI Toolkits User Guide](https://software.intel.com/content/www/us/en/develop/documentation/using-vs-code-with-intel-oneapi/top.html). -### On a Linux* System - -1. Generate the `Makefile` by running `cmake`. - ``` - mkdir build - cd build - ``` - To compile for the Intel® PAC with Intel Arria® 10 GX FPGA, run `cmake` using the command: - ``` - cmake .. - ``` - Alternatively, to compile for the Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX), run `cmake` using the command: - - ``` - cmake .. -DFPGA_DEVICE=intel_s10sx_pac:pac_s10 - ``` - You can also compile for a custom FPGA platform. Ensure that the board support package is installed on your system. Then run `cmake` using the command: - ``` - cmake .. -DFPGA_DEVICE=: - ``` - -2. Compile the design through the generated `Makefile`. The following build targets are provided, matching the recommended development flow: - - * Compile for emulation (fast compile time, targets emulated FPGA device): - ``` - make fpga_emu - ``` - * Compile for simulation (fast compile time, targets simulator FPGA device): - ``` - make fpga_sim - ``` - * Generate the optimization report: - ``` - make report - ``` - * Compile for FPGA hardware (longer compile time, targets FPGA device): - ``` - make fpga - ``` -3. (Optional) As the above hardware compile may take several hours to complete, FPGA precompiled binaries (compatible with Linux* Ubuntu* 18.04) can be downloaded here. +### Configure the build system + +Create and go to a build directory +``` +mkdir build +cd build +``` + +#### On a Linux* System + +To configure the build system for the Intel® PAC with Intel Arria® 10 GX FPGA, run `cmake` using the command: +``` +cmake .. +``` +Alternatively, to configure the build system for the Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX), run `cmake` using the command: -### On a Windows* System - -1. Generate the `Makefile` by running `cmake`. - ``` - mkdir build - cd build - ``` - To compile for the Intel® PAC with Intel Arria® 10 GX FPGA, run `cmake` using the command: - ``` - cmake -G "NMake Makefiles" .. - ``` - Alternatively, to compile for the Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX), run `cmake` using the command: - - ``` - cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=intel_s10sx_pac:pac_s10 - ``` - You can also compile for a custom FPGA platform. Ensure that the board support package is installed on your system. Then run `cmake` using the command: - ``` - cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=: - ``` - -2. Compile the design through the generated `Makefile`. The following build targets are provided, matching the recommended development flow: - - * Compile for emulation (fast compile time, targets emulated FPGA device): - ``` - nmake fpga_emu - ``` - * Compile for simulation (fast compile time, targets simulator FPGA device): - ``` - nmake fpga_sim - ``` - * Generate the optimization report: - ``` - nmake report - ``` - * Compile for FPGA hardware (longer compile time, targets FPGA device): - ``` - nmake fpga - ``` +``` +cmake .. -DFPGA_DEVICE=intel_s10sx_pac:pac_s10 +``` +You can also configure the build system for a custom FPGA platform. Ensure that the board support package is installed on your system. Then run `cmake` using the command: +``` +cmake .. -DFPGA_DEVICE=: +``` + +#### On a Windows* System +To configure the build system for the Intel® PAC with Intel Arria® 10 GX FPGA, run `cmake` using the command: +``` +cmake -G "NMake Makefiles" .. +``` +Alternatively, to configure the build system for the Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX), run `cmake` using the command: + +``` +cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=intel_s10sx_pac:pac_s10 +``` +You can also configure the build system for a custom FPGA platform. Ensure that the board support package is installed on your system. Then run `cmake` using the command: +``` +cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=: +``` + +### Compile the design + + +* Compile for emulation (fast compile time, targets emulated FPGA device): + ``` + cmake --build . --target fpga_emu + ``` +* Compile for simulation (fast compile time, targets simulator FPGA device): + ``` + cmake --build . --target fpga_sim + ``` +* Generate the optimization report: + ``` + cmake --build . --target report + ``` +* Compile for FPGA hardware (longer compile time, targets FPGA device): + ``` + cmake --build . --target fpga + ``` + +3. (Optional) As the above hardware compile may take several hours to complete, FPGA precompiled binaries (compatible with Linux* Ubuntu* 18.04) can be downloaded here. > **Note**: The Intel® PAC with Intel Arria® 10 GX FPGA and Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX) do not support Windows*. Compiling to FPGA hardware on Windows* requires a third-party or custom Board Support Package (BSP) with Windows* support. > **Note**: If you encounter any issues with long paths when compiling under Windows*, you may have to create your ‘build’ directory in a shorter path, for example c:\samples\build. You can then run cmake from that directory, and provide cmake with the full path to your sample directory. ### Troubleshooting -If an error occurs, you can get more details by running `make` with -the `VERBOSE=1` argument: -``make VERBOSE=1`` +If an error occurs, you can get more details by running `cmake` with +the `-- VERBOSE=1` argument: +e.g. ``cmake --build . --target fpga_emu -- VERBOSE=1`` For more comprehensive troubleshooting, use the Diagnostics Utility for Intel® oneAPI Toolkits, which provides system checks to find missing dependencies and permissions errors. @@ -233,20 +213,20 @@ You can also check the achieved system fMAX to verify the earlier cal ## Running the Sample 1. Run the sample on the FPGA emulator (the kernel executes on the CPU): - ``` - ./loop_unroll.fpga_emu (Linux) - loop_unroll.fpga_emu.exe (Windows) - ``` + ``` + ./loop_unroll.fpga_emu (Linux) + loop_unroll.fpga_emu.exe (Windows) + ``` 2. Run the sample on the FPGA simulator device: - ``` - ./loop_unroll.fpga_sim (Linux) - loop_unroll.fpga_sim.exe (Windows) - ``` + ``` + ./loop_unroll.fpga_sim (Linux) + loop_unroll.fpga_sim.exe (Windows) + ``` 3. Run the sample on the FPGA device: - ``` - ./loop_unroll.fpga (Linux) - loop_unroll.fpga.exe (Windows) - ``` + ``` + ./loop_unroll.fpga (Linux) + loop_unroll.fpga.exe (Windows) + ``` ### Example of Output ``` diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Features/loop_unroll/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/Tutorials/Features/loop_unroll/src/CMakeLists.txt deleted file mode 100644 index 91f8949f66..0000000000 --- a/DirectProgramming/DPC++FPGA/Tutorials/Features/loop_unroll/src/CMakeLists.txt +++ /dev/null @@ -1,90 +0,0 @@ -set(SOURCE_FILE loop_unroll.cpp) -set(TARGET_NAME loop_unroll) -set(EMULATOR_TARGET ${TARGET_NAME}.fpga_emu) -set(SIMULATOR_TARGET ${TARGET_NAME}.fpga_sim) -set(FPGA_TARGET ${TARGET_NAME}.fpga) - -# FPGA board selection -if(NOT DEFINED FPGA_DEVICE) - set(FPGA_DEVICE "intel_a10gx_pac:pac_a10") - message(STATUS "FPGA_DEVICE was not specified.\ - \nConfiguring the design to run on the default FPGA board ${FPGA_DEVICE} (Intel(R) PAC with Intel Arria(R) 10 GX FPGA). \ - \nPlease refer to the README for information on board selection.") -else() - message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}") -endif() - -# This is a Windows-specific flag that enables exception handling in host code -if(WIN32) - set(WIN_FLAG "/EHsc") -endif() - -# A SYCL ahead-of-time (AoT) compile processes the device code in two stages. -# 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). -# 2. The "link" stage invokes the compiler's FPGA backend before linking. -# For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -DFPGA_EMULATOR") -set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga") -set(SIMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -Xssimulation -DFPGA_SIMULATOR") -set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") -set(HARDWARE_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga") -set(HARDWARE_LINK_FLAGS "-fsycl -fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") -# use cmake -D USER_HARDWARE_FLAGS= to set extra flags for FPGA simulator compilation and backend compilation - -############################################################################### -### FPGA Emulator -############################################################################### -# To compile in a single command: -# icpx -fsycl -fintelfpga -DFPGA_EMULATOR loop_unroll.cpp -o loop_unroll.fpga_emu -# CMake executes: -# [compile] icpx -fsycl -fintelfpga -DFPGA_EMULATOR -o loop_unroll.cpp.o -c loop_unroll.cpp -# [link] icpx -fsycl -fintelfpga loop_unroll.cpp.o -o loop_unroll.fpga_emu -add_executable(${EMULATOR_TARGET} ${SOURCE_FILE}) -target_include_directories(${EMULATOR_TARGET} PRIVATE ../../../../include) -set_target_properties(${EMULATOR_TARGET} PROPERTIES COMPILE_FLAGS "${EMULATOR_COMPILE_FLAGS}") -set_target_properties(${EMULATOR_TARGET} PROPERTIES LINK_FLAGS "${EMULATOR_LINK_FLAGS}") -add_custom_target(fpga_emu DEPENDS ${EMULATOR_TARGET}) - -############################################################################### -### FPGA Simulator -############################################################################### -# To compile in a single command: -# icpx -fintelfpga -Xssimulation -Xsghdl -Xstarget= -DFPGA_SIMULATOR loop_unroll.cpp -o loop_unroll.fpga_sim -# CMake executes: -# [compile] icpx -fintelfpga -Xssimulation -DFPGA_SIMULATOR -o loop_unroll.cpp.o -c loop_unroll.cpp -# [link] icpx -fintelfpga -Xssimulation -Xsghdl -Xstarget= loop_unroll.cpp.o -o loop_unroll.fpga_sim -add_executable(${SIMULATOR_TARGET} ${SOURCE_FILE}) -target_include_directories(${SIMULATOR_TARGET} PRIVATE ../../../../include) -set_target_properties(${SIMULATOR_TARGET} PROPERTIES COMPILE_FLAGS "${SIMULATOR_COMPILE_FLAGS}") -set_target_properties(${SIMULATOR_TARGET} PROPERTIES LINK_FLAGS "${SIMULATOR_LINK_FLAGS}") -add_custom_target(fpga_sim DEPENDS ${SIMULATOR_TARGET}) - -############################################################################### -### Generate Report -############################################################################### -# To compile manually: -# icpx -fsycl -fintelfpga -Xshardware -Xstarget= -fsycl-link=early loop_unroll.cpp -o loop_unroll_report.a -set(FPGA_EARLY_IMAGE ${TARGET_NAME}_report.a) -# The compile output is not an executable, but an intermediate compilation result unique to SYCL. -add_executable(${FPGA_EARLY_IMAGE} ${SOURCE_FILE}) -target_include_directories(${FPGA_EARLY_IMAGE} PRIVATE ../../../../include) -add_custom_target(report DEPENDS ${FPGA_EARLY_IMAGE}) -set_target_properties(${FPGA_EARLY_IMAGE} PROPERTIES COMPILE_FLAGS "${HARDWARE_COMPILE_FLAGS}") -set_target_properties(${FPGA_EARLY_IMAGE} PROPERTIES LINK_FLAGS "${HARDWARE_LINK_FLAGS} -fsycl-link=early") -# fsycl-link=early stops the compiler after RTL generation, before invoking Quartus® - -############################################################################### -### FPGA Hardware -############################################################################### -# To compile in a single command: -# icpx -fsycl -fintelfpga -Xshardware -Xstarget= loop_unroll.cpp -o loop_unroll.fpga -# CMake executes: -# [compile] icpx -fsycl -fintelfpga -o loop_unroll.cpp.o -c loop_unroll.cpp -# [link] icpx -fsycl -fintelfpga -Xshardware -Xstarget= loop_unroll.cpp.o -o loop_unroll.fpga -add_executable(${FPGA_TARGET} EXCLUDE_FROM_ALL ${SOURCE_FILE}) -target_include_directories(${FPGA_TARGET} PRIVATE ../../../../include) -add_custom_target(fpga DEPENDS ${FPGA_TARGET}) -set_target_properties(${FPGA_TARGET} PROPERTIES COMPILE_FLAGS "${HARDWARE_COMPILE_FLAGS}") -set_target_properties(${FPGA_TARGET} PROPERTIES LINK_FLAGS "${HARDWARE_LINK_FLAGS} -reuse-exe=${CMAKE_BINARY_DIR}/${FPGA_TARGET}") -# The -reuse-exe flag enables rapid recompilation of host-only code changes. -# See DPC++FPGA/GettingStarted/fast_recompile for details. diff --git a/DirectProgramming/DPC++FPGA/Tutorials/Features/loop_unroll/src/loop_unroll.cpp b/DirectProgramming/DPC++FPGA/Tutorials/Features/loop_unroll/src/loop_unroll.cpp index d94c07124c..07e4d7ea0a 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/Features/loop_unroll/src/loop_unroll.cpp +++ b/DirectProgramming/DPC++FPGA/Tutorials/Features/loop_unroll/src/loop_unroll.cpp @@ -27,16 +27,16 @@ void VecAdd(const std::vector &summands1, size_t array_size) { -#if defined(FPGA_EMULATOR) - ext::intel::fpga_emulator_selector device_selector; -#elif defined(FPGA_SIMULATOR) - ext::intel::fpga_simulator_selector device_selector; -#else - ext::intel::fpga_selector device_selector; +#if FPGA_SIMULATOR + auto selector = sycl::ext::intel::fpga_simulator_selector_v; +#elif FPGA_HARDWARE + auto selector = sycl::ext::intel::fpga_selector_v; +#else // #if FPGA_EMULATOR + auto selector = sycl::ext::intel::fpga_emulator_selector_v; #endif try { - queue q(device_selector, fpga_tools::exception_handler, + queue q(selector, fpga_tools::exception_handler, property::queue::enable_profiling{}); buffer buffer_summands1(summands1);