perf(ggml/hip): speed up fp3 ROCMFPX matvec (Q3_0_ROCMFPX) on RDNA

[DeanoC]

Summary

Optimizes the Q3_0_ROCMFPX (fp3, 3.5 bpw) vec-dot — the hottest GPU kernel in
DeepSeek-V4-Flash DSpark decode, since the expert down-projections are stored in
fp3. Three HIP-only, fp3-only changes, each verified bit-identical to the code
it replaces. All other quant types and all non-HIP builds are untouched.

Depends on (and measured against)

This stacks on two open upstream PRs — both are prerequisites and the benchmark base:

• feat(ds4): add DSpark speculative decoding (+27% on Strix Halo) Luce-Org/lucebox#496 — DSpark speculative runtime (the decode path the benchmark exercises; head df6f907, an exact ancestor of the base).
• perf(ggml/hip): add batched ROCmFPX MMQ Luce-Org/lucebox#513 — batched ROCmFPX MMQ (the fp3 verify-batch matmul; head ad73cb8, an exact ancestor of the base). The ds_swizzle and decode changes touch both this MMQ path and the single-token MMVQ path.

The vec_dot_rocmfpx_fp3_q8_1 / fp3 MMQ kernels optimized here come from the vendored ROCmFPX support (byte-safe / fused fp3 decode, cf. Luce-Org#503). The PR base branch base/ds4-mmq-spec-b9e5804 is exactly #496 merged with #513; only the 3 kernel changes below differ from it.

Changes (single concern: the fp3 HIP matvec)

1. Vectorized fp3 code decode (vecdotq.cuh) — decode 4 fp3 codes with a single
   v_perm_b32 over an 8-byte LUT (rocmfpx_pack4_fp3_bits12_vec_cuda) instead of 4
   scalar decodes + make_char4; extract the 12-/24-bit code window with one
   dword-splice instead of a per-bit OR loop.
2. Folded epilogue in vec_dot_rocmfpx_fp3_q8_1 — the MMVQ launcher only ever emits
   even iqs, so both VDR groups always land in the same half-block; fold to a single
   accumulator and select the half-block scale once, dropping a dead dp4a + branch and
   a redundant scale conversion/fma from the per-block epilogue.
3. ds_swizzle warp reduction (mmvq.cu) — reduce the fp3 partial sums with a
   bitmask-mode ds_swizzle butterfly instead of the ds_bpermute lowering that HIP
   emits for warp_reduce_sum; identical {16,8,4,2,1} reduction order and float adds.

Benchmark

• Hardware: AMD Ryzen AI Max (gfx1151 / Strix Halo, RDNA3.5 APU), ROCm 7.2.4, unified memory.
• Model: DeepSeek-V4-Flash, native ROCMFPX GGUF (ROCMFP2 experts / fp3 down-proj / ROCMFP4 attention).
• Workload: DSpark speculative decode (--verify-width 4), greedy (temperature 0), fixed 160-token prompt.
• Clock control: mclk pinned to 1000 MHz (rocm-smi --setmclk 2). sclk is not lockable on this APU (the SMU firmware ignores perf-determinism, DPM-mask, and ceiling controls), so each config runs 2 full-length warm-ups to reach steady clock, then 7 measured reps, and we report the achieved sclk so the comparison is matched-clock.
• Base: #496 merged with #513 (branch base/ds4-mmq-spec-b9e5804, this PR's parent); only the 3 kernel changes differ.

Config	decode tok/s (median, n=7)	accept_rate	achieved sclk (MHz)
base	21.7 (± 0.14)	0.78	1786
this PR	24.3 (± 0.07)	0.78	1843

+12.0% median throughput; +11.0% at matched clock (at ~1855 MHz: base 21.9, PR 24.3).
accept_rate unchanged (0.78). Reproduced across two independent runs (+12.6%, +12.0%).

Correctness

Greedy output is byte-identical to base across 8 diverse prompts (code, algorithms,
exact arithmetic, logic, long-form, JSON, factual recall, repetition) on both decode
paths — the single-token MMVQ path and the DSpark verify (MMQ) path — SHA-256 of each
completion matches per prompt. Every transformation is annotated in-code with its
bit-identity argument. The one exception is a sign-of-zero corner in the epilogue fold,
which the cross-lane reduction washes out; it is documented at the call site.

Scope

HIP + GGML_TYPE_Q3_0_ROCMFPX only, gated by #if defined(GGML_USE_HIP) plus a
constexpr type check. No effect on CUDA builds or any other quant type. Apache-2.0.

[DeanoC]

Superseded by #21, which squashes this and the stacked follow-up into a single review-friendly PR (same final kernel state, one diff off b9e5804). Closing to keep review in one place.