Various improvements#561
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whitequark merged 5 commits intoGlasgowEmbedded:mainfrom Apr 20, 2024
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This happens often when hitting ^C, but did not happen when I committed this code originally. Possibly the cause is the use of a newer Python version.
This significantly improves throughput, in particular with `recv`.
By default (without a send buffer configured), the `write` call never blocks, and there scarcely be a reason for it to block on a modern system that can process many more packets with much more data than we can put into it. However, by using the loop to detect readiness, this function would incur latency in the calling asyncio task each time it was used, even if the write would succeed, which impacted throughput.
Wide counters (24-bit and wider) are problematic on the fairly slow iCE40 architecture, and this module allows using counters of any width by pipelining them. Co-authored-by: Wanda <wanda@phinode.net>
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This is a rollup PR of several pending improvements that I have:
asignalbug which would sometimes show a backtrace on ^Cregistersmodule that improves compatibility with components and reduces boilerplate, extracted from [Addon in validation] Add Ram-Pak support #483