GlasgowEmbedded · pd0wm · Aug 1, 2025 · Aug 4, 2025 · Aug 4, 2025 · Aug 11, 2025
@@ -9,3 +9,4 @@ MCU debugging
     :maxdepth: 3
 
     arm7
+    superh
@@ -0,0 +1,10 @@
+``debug-superh-aud``
+====================
+
+CLI reference
+-------------
+
+.. _applet.debug.superh.aud:
+
+.. autoprogram:: glasgow.applet.debug.superh.aud:AUDApplet._get_argparser_for_sphinx("debug-superh-aud")
+    :prog: glasgow run debug-superh-aud
Original file line number	Diff line number	Diff line change
Expand Up		@@ -9,3 +9,4 @@ MCU debugging
		:maxdepth: 3

		arm7
		superh
Copy link Copy Markdown Member whitequark Aug 4, 2025 • edited Loading Choose a reason for hiding this comment The reason will be displayed to describe this comment to others. Learn more. I think the appropriate taxon is program even though it is technically using an interface with "Debug" in its name: The program taxon groups applets implementing interfaces to memory technology devices (volatile and non-volatile) that are directly connected to programmable logic, such as a microcontroller or a gate array. I tried to figure out how you would make a debugger using AUD-II and it's not clear to me that you can. The built-in modes are tracing and arbitrary read/write. You have a breakpoint module (UBC) that seems programmable via monitoring mode which could support single-stepping and breakpoints. There is however no way to get an arbitrary CPU register via AUD-II (or execute an arbitrary instruction, or even just get the value of R15), so you'd need help from the firmware: an ISR that dumps the CPU context into some predefined RAM area that is used for communicating with the debugger. Even then, UBC has no way to tell which breakpoint has fired on any particular cycle, so even though it supports data breakpoints you can't use it for watchpoints: you wouldn't know whether a breakpoint or a watchpoint has fired, which breaks single-stepping. You could work around that by adding an SH-2A emulator and an architecture model and evaluating every configured breakpoint/watchpoint against the post-breakpoint architectural state, if you wanted to create an abomination and had a vast excess of free time on your hands. I think it's safe to say nobody will ever contribute a debugger for this chip. Copy link Copy Markdown Author pd0wm Aug 5, 2025 Choose a reason for hiding this comment The reason will be displayed to describe this comment to others. Learn more. Some chips don't have physical JTAG pins, and only rely on the AUD interface for flashing and debugging. They probably have some very cursed way of doing this, but I'm not spending €1800 to find out. So indeed safe to say this won't be added anytime soon, at least not before H-UDI support. Copy link Copy Markdown Member whitequark Aug 5, 2025 Choose a reason for hiding this comment The reason will be displayed to describe this comment to others. Learn more. Do you happen to know a part number for one of those chips/ I'm curious.