Pinned Loading

1. audioStream audioStream Public

   A simple project for audio streaming on an FPGA using a CDC FIFO.

   SystemVerilog

2. sobelFilter sobelFilter Public

   Image filter accelerator on ice breaker FPGA

   Jupyter Notebook

3. uartAXIBridge uartAXIBridge Public

   A UART-driven AXI RAM verification project using SystemVerilog RTL and cocotb.

   SystemVerilog 1

4. redstoneCore redstoneCore Public

   A RISC-V core.

   Assembly

5. systolicArray systolicArray Public

   SystemVerilog