feat: DFlash support for tensor-parallel Qwen3.6 targets

[jkyamog]

Extend Qwen3.6 tensor parallelism from target-only autoregressive generation
to DFlash speculative decoding, including the device-local state and transfer
optimizations previously planned as a separate follow-up.

The draft remains on its explicit local device while target verification runs
through the TP meta backend. The change gathers complete target features for
the draft and extends rollback, recurrent state, snapshots, and prefix-cache
restore to split tensors.

Changes

• Snapshot and restore recurrent TP state directly between each rank's GPU
  tensors instead of gathering it through host memory.
• Restore split SSM and convolution state on-device and synchronize once per
  rank after rollback.
• Decide DDTree eligibility before projection, avoiding duplicate LM-head
  execution.
• Run draft top-K on rank 0's mirrored GPU logits.
• Use the optimized rollback threshold for TP while preserving upstream's
  configurable rollback policy for single-device and layer-split execution.
• Batch feature-ring synchronization with one get_2d and one set_2d per
  non-wrapping run. Long prefills and prefix restores no longer perform two
  host/device transfers and stream synchronizations per token.
• Add opt-in aggregate phase timing with DFLASH_TP_PROFILE=1.

The stacked target branch also contains the review fixes for invalid device
counts, repeated split-state propagation and copies, multi-segment debug
output, legacy callback compatibility, and NaN-safe fallback all-reduce.

Verification

• Full native CUDA build and 19/19 CTest targets pass on main@f258c4a.
• Chain speculative generation, DDTree, and fast rollback pass.
• Streaming forced-function output produces structured tool_calls.
• A 26,704-token prefix snapshot is committed, found, and restored for a
  26,758-token OpenClaw request. The repeated request's prefill drops from
  21.4 s to 0.1 s and produces byte-identical output.
• The deterministic 1,024-token OpenClaw control at 98,304 context produces
  SHA-256 3614d727a950d5416a42b5e0e3713054e59ddc9a0365fb4ac1a2cbd198f5964f,
  matching the saved pre-optimization and target-only continuation.
• The final full matrix completed without warnings for every viable row. TP
  plus draft peaked at 15,208/12,640 MiB for Q5 and 20,742/18,176 MiB for Q6
  on the two 3090s.

Sustained performance

Hardware: RTX 5090 plus an NVLink-connected RTX 3090 pair at stock power.
Workload: 26,758 prompt tokens, 1,024 generated tokens, 98,304 context, Q8 KV,
Q8 draft, DDTree budget 16, no prefix cache, and a 60-second cooldown between
rows. These are single runs on the final rebased head. Every row uses 98,304
context except the explicitly marked Q6/5090 capacity row.

Model / configuration	DFlash TG	AR TG	Relative	Prefill	Decode	Total
Q5, RTX 5090	126.2 tok/s	59.5 tok/s	2.12x	10.3 s	8.1 s	18.4 s
Q5, 2x3090 layer split	28.7 tok/s	20.6 tok/s	1.39x	44.7 s	35.7 s	81.1 s
Q5, 2x3090 TP + NVLink	86.5 tok/s	40.4 tok/s	2.14x	20.7 s	11.8 s	32.5 s
Q5, 2x3090 TP, P2P disabled	75.5 tok/s	38.9 tok/s	1.94x	29.2 s	13.6 s	42.8 s
Q6, RTX 5090, 32,768 context	80.1 tok/s	48.7 tok/s	1.64x	10.3 s	12.8 s	23.1 s
Q6, 2x3090 layer split	21.8 tok/s	17.7 tok/s	1.23x	46.0 s	47.0 s	93.8 s
Q6, 2x3090 TP + NVLink	60.5 tok/s	34.8 tok/s	1.74x	21.4 s	16.9 s	38.4 s
Q6, 2x3090 TP, P2P disabled	55.2 tok/s	34.3 tok/s	1.61x	29.9 s	18.6 s	48.5 s

Q5 performs 192 target forwards for 192 DDTree steps; Q6 performs 190 for
190. The optimized Q5 NVLink phase profile is:

draft=2.379s project=0.407s snapshot=0.354s verify=8.430s
rollback=0.192s replay=0.000s feature=0.061s accounted=11.823s

Q5 TP is 3.01x faster than Q5 layer split and Q6 TP is 2.78x faster than Q6
layer split. Direct-P2P and P2P-disabled TP runs for both quants produced the
same byte-identical output hash shown above.

Q5 on one 24 GB 3090 failed while allocating a 1,411 MiB rollback-cache buffer
after reaching 23,286 MiB. The server logged prefill_failed, but the HTTP
layer returned 200 with empty assistant content and finish_reason=stop; that
error-mapping behavior is separate from this TP PR. Q6 on the 5090 aborts with
CUDA OOM at both 98,304 and 65,536 context, but succeeds at 32,768 context with
a 31,569 MiB peak. That constrained run produced the same assistant-content
hash as Q5 on the 5090:
ac5279693a48ecc1b5e19daeadda5872f03bb47e40d589c6a40524db0596ef34.

HIP was not compiled on this NVIDIA host because ROCm is not installed. The
new pointer-query calls use the existing CUDA/HIP compatibility header.

[cubic-dev-ai]

All reported issues were addressed across 24 files

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[jkyamog]

fyi: I have been using this for more than a day, likely used around 20-50M tokens already. So far its been good, saw a parser bug but not related to this PR.

• Hardware: 2x RTX 3090 24 GB
• Power limit: 300 W per GPU
• Target: Qwen3.6-27B-Q6_K.gguf
• Draft: dflash-draft-3.6-q8_0.gguf
• Target execution: tensor parallel across both GPUs
• CUDA peer access/NVLink: enabled
• Context: 262,144 tokens
• Default max output: 16,384 tokens
• Thinking limit: 15,488 tokens
• KV cache: Q8_0 K and V
• DFlash/DDTree budget: 22
• Draft SWA: 2,048
• Flash-attention window: disabled/full-context attention
• Prefix-cache slots: 4
• Prefill-cache slots: 0
• Fast rollback: enabled

This not too far from my 5090, but the 2x 3090 being 48gb has 2x the context size.