Fix FastDivmod divisor SSA transport for kernel regions (#3243)#3246
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zhils wants to merge 1 commit into
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Fix FastDivmod divisor SSA transport for kernel regions (#3243)#3246zhils wants to merge 1 commit into
zhils wants to merge 1 commit into
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Expose encoded divisor plus scalar divisor IR through FastDivmodDivisor::__extract_mlir_values__ and rebuild .divisor from region-local SSA in __new_from_mlir_values__. Update persistent tile schedulers to slice FDD tail by extract_mlir_values length. Add CuTeDSL compile regression derived from upstream repro. Co-authored-by: Cursor <cursoragent@cursor.com>
questa-wang
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May 20, 2026
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LGTM. Thanks for the fix.
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Hi @zhils, thanks a lot for putting up this fix! We've been tracking the same root cause internally and have landed a broader patch that touches additional consumers beyond what's visible in the public tree, plus a small fix avoid re-emitting IR on the device side during reconstruction. |
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Fixes #3243
Expose encoded divisor plus scalar divisor IR through
FastDivmodDivisor::__extract_mlir_values__and rebuild.divisorfrom region-local SSA in__new_from_mlir_values__. Update persistent tile schedulers to slice the FastDivmod tail usingextract_mlir_valueslength. Add a CuTeDSL compile regression aligned with the issue repro.Test plan
pytest test/examples/CuTeDSL/test_fast_divmod_divisor_param_transport.py