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PranathiSReddy25/README.md

💫 About Me:

👋 Hi, I'm Pranathi!

🎓 Electronics and Communication Engineering undergraduate at BMS College of Engineering.

💡 Passionate about RTL Design, Digital Design, Computer Architecture, FPGA Design, and VLSI.

🚀 Currently building digital systems in Verilog HDL and strengthening my understanding of processor design through hands-on projects

🚀 Featured Projects

⭐ RISC-V 5-Stage Pipelined Processor

⭐ UART FIFO with CRC Error Detection

⭐ ATM Controller using FSM

Languages • Verilog HDL • C • Python

Tools • Xilinx Vivado • Git

Areas of Interest • RTL Design • Digital Design • Computer Architecture • FPGA • VLSI

📊 GitHub Stats:



Popular repositories Loading

  1. Sorting_Network_8Input_Verilog Sorting_Network_8Input_Verilog Public

    8-input sorting network implemented in Verilog HDL using comparator modules.

    Verilog 1

  2. PranathiSReddy25 PranathiSReddy25 Public

  3. rv32i-5stage-pipelined-processor rv32i-5stage-pipelined-processor Public

    32-bit 5-stage pipelined RISC-V (RV32I) processor in Verilog HDL with hazard detection, data forwarding, branch handling, and FPGA synthesis using Xilinx Vivado.