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Assigning a packet into its ring buffer slot pulls that slot's cache line in for ownership and dirties it, which buys nothing: the packet processor is the only other reader and it fetches the slot over the fabric anyway. Copy the 60 body bytes with non-temporal stores instead, so they land straight in the write-combining buffer, and keep publishing the header with the existing release store once an sfence has drained that buffer. The header dword stays out of the copy, so the slot holds the invalid header the packet processor left behind until the body has arrived. Covers kernel dispatch, barrier-AND and barrier-value packet submission.
saleelk
requested review from
chrispaquot,
mangupta and
rakesroy
as code owners
September 2, 2026 05:48
MOVDIR64B stores all 64 bytes of a packet as one atomic write, so the packet processor can only observe the slot's old invalid header or the complete new packet -- there is no window where a valid header sits over a body that has not landed yet. It also collapses the non-temporal path's body copy, sfence and separate header store into a single instruction. Detect it from CPUID leaf 7 sub-leaf 0 (ECX bit 28), cache the result, and take that path whenever DEBUG_CLR_USE_MOVDIR64B is non-zero, which it is by default. Hosts without the instruction keep the non-temporal stores. Neither path needs a fence before the doorbell, since ROCr sfences before it writes the hardware doorbell.
lmoriche
reviewed
Sep 15, 2026
lmoriche
reviewed
Sep 15, 2026
| // ================================================================================================ | ||
| static inline bool useMovdir64b() { | ||
| #if defined(ATI_ARCH_X86) && defined(_LP64) | ||
| static const bool enabled = DEBUG_CLR_USE_MOVDIR64B != 0 && Os::hasMovdir64b(); |
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Might be good to add a log info so we know what was detected by the runtime.
static auto enabled = []() {
auto flag = DEBUG_CLR_USE_MOVDIR64B != 0 && Os::hasMovdir64b();
LOG_INFO ...
return flag;
}();
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Assigning a packet into its ring buffer slot pulls that slot's cache line in for ownership and dirties it, which buys nothing: the packet processor is the only other reader and it fetches the slot over the fabric anyway.
Copy the 60 body bytes with non-temporal stores instead, so they land straight in the write-combining buffer, and keep publishing the header with the existing release store once an sfence has drained that buffer. The header dword stays out of the copy, so the slot holds the invalid header the packet processor left behind until the body has arrived. Covers kernel dispatch, barrier-AND and barrier-value packet submission.
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