[AMD][MI35X] Bump Qwen3.5 MXFP4 MI355X SGLang AgentX to v0.5.18 and retune all-reduce, prefill, and CUDA graph

[yichiche]

Motivation

qwen3.5-fp4-mi355x-sglang-agentic-mtp is still on lmsysorg/sglang-rocm:v0.5.17-rocm720-mi35x-20260818, and three of its launch knobs are out of step with the sibling recipes on the same cluster.

First, all-reduce. The script correctly omits --enable-aiter-allreduce-fusion (removed in #2562 for TP2/EP2 EAGLE rank consistency) but never sets ROCM_QUICK_REDUCE_QUANTIZATION, so multi-GPU collectives run unquantized custom all-reduce. The published SGLang cookbook recipe for MXFP4 on MI355X calls for INT8-quantized quick all-reduce.

Second, the prefill budget is double the B200 sibling: --max-prefill-tokens 32768 / --chunked-prefill-size 32768 here versus 16384 / 16384 in benchmarks/single_node/agentic/qwen3.5_fp4_b200_sglang_mtp.sh.

Third, the decode CUDA graph is undersized for the batch the scheduler actually builds. --max-running-requests is 2*CONC, but the graph was only captured to min(CONC, 64), so every decode batch above CONC fell onto the eager path.

Modifications

Bump image on qwen3.5-fp4-mi355x-sglang-agentic-mtp to lmsysorg/sglang-rocm:v0.5.18-rocm720-mi35x-20260825. The model, runner, and search space are untouched.

In benchmarks/single_node/agentic/qwen3.5_fp4_mi355x_sglang_mtp.sh, add export ROCM_QUICK_REDUCE_QUANTIZATION=INT8 alongside the existing aiter exports. The two all-reduce paths are mutually exclusive in SGLang: the AITER fused AR+RMSNorm path is gated on --enable-aiter-allreduce-fusion, and only with it off do collectives fall back to custom all-reduce, where the quick-reduce regime is read. Since this arm already omits the fusion flag, the env takes effect with no other launch change.

Lower --max-prefill-tokens and --chunked-prefill-size from 32768 to 16384, matching the B200 sibling.

Capture the decode CUDA graph to min(2*CONC, 128) instead of min(CONC, 64), so it covers --max-running-requests. The expression and the 128 cap are taken verbatim from the sibling MI355X AgentX recipe benchmarks/single_node/agentic/dsv4_fp4_mi355x_sglang_mtp.sh, which already runs this idiom on cluster:mi355x-amds.

Append the corresponding perf-changelog.yaml trigger.

Accuracy Tests

No accuracy-affecting logic changes in this repo. INT8 quick all-reduce quantizes the collective payload, so it is not bit-identical to the unquantized path; the AgentX eval rows continue to run real target-model verification and will show whether that matters. The prefill and CUDA-graph knobs change scheduling and kernel launch shape, not what is computed.

Benchmarking

Repo validation was run locally:

• python3 -m pytest utils/matrix_logic/ -q → 232 passed.
• bash -n benchmarks/single_node/agentic/qwen3.5_fp4_mi355x_sglang_mtp.sh → clean.
• python3 utils/matrix_logic/generate_sweep_configs.py full-sweep --config-files configs/amd-master.yaml --model-prefix qwen3.5 --precision fp4 --scenario-type agentic-coding → 16 configs, all on v0.5.18-rocm720-mi35x-20260825.
• Hand-evaluated the new CUDA-graph expression across the config's conc-list (TP2 1,4,8,12,16,20; TP4 1,4,8,12,16,20,24,28,32,40): it yields 2*CONC at every point, so the 128 cap never binds in the current sweep.

End-to-end MI355X AgentX numbers will come from the sweep triggered on this PR (full-sweep-fail-fast). Three knobs plus an image move together here, so the resulting numbers are not attributable to any single one of them; if the arm regresses, the all-reduce regime is the first knob to isolate.

Conflicts

#2693 touches the same script, the same config block, and also appends to perf-changelog.yaml, so the changelog append will collide and whichever lands second needs a rebase. The changes themselves are complementary.

Two notes for whoever reviews alongside #2693. That PR raises the TP4 concurrency ceiling to 64 via its HiCache arms — at CONC=64 the new min(2*CONC, 128) lands exactly on the 128 cap, which is the intended behaviour but worth knowing. And #2693's stated motivation is MI355X/B200 comparability: the B200 sibling still captures to min(CONC, 64), so this PR re-introduces a difference on that knob. It is harness tuning rather than a deployment-defining server arg, but it is a real difference and should not be discovered by surprise.

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Note

Medium Risk
Benchmark harness and collective quantization changes affect published MI355X AgentX throughput/latency and may not be bit-identical to the prior unquantized all-reduce path; accuracy is validated only via existing eval runs.

Overview
Updates qwen3.5-fp4-mi355x-sglang-agentic-mtp to SGLang ROCm v0.5.18 and retunes the AgentX launch script so MI355X MXFP4 serving matches sibling recipes and the published cookbook.

The benchmark script now routes multi-GPU collectives through INT8 ROCm quick all-reduce (ROCM_QUICK_REDUCE_QUANTIZATION), pins EAGLE draft-extend off unified AITER attention (SGLANG_AITER_UNIFIED_DRAFT_EXTEND=0), halves prefill limits to 16384 (--max-prefill-tokens / --chunked-prefill-size, aligned with the B200 arm), and sizes decode CUDA graphs to min(2×CONC, 128) so graph capture covers --max-running-requests at 2×CONC instead of undersized min(CONC, 64) eager fallbacks.

configs/amd-master.yaml only changes the container image; perf-changelog.yaml documents the retune for sweep invalidation.

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Changelog breaks append-only bytes

Medium Severity

The new perf-changelog.yaml entry deletes historical blank-line separator bytes between existing entries instead of leaving the prior file as an exact prefix. That file is byte-sensitive, so the mutation breaks the append-only prefix that sweep gating and reuse checks require.

 

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see unofficial run visualizer at https://inferencex.semianalysis.com/inference?unofficialRun=33026661557
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