UART peripheral#154
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Integrate UART peripheral with the core to load instruction and read the memory out
🔧 DE1-SoC Synthesis Report Summary Diff
Comparing synthesis results from main branch vs. this PR |
TheDeepestSpace
commented
Mar 9, 2026
| LEDR_ADDRESS: read_data = {22'b0, LEDR}; | ||
| DBG_PC_ADDR: read_data = dbg_pc; | ||
| default: begin | ||
| if (dbg_reg_hit && (dbg_reg_idx < 5'd32)) read_data = dbg_regs[dbg_reg_idx]; |
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i think there's a construct that looks like case (address) inside that allows specifying ranges of values in the case's arms. I think it should be synthesizable, not sure how efficient though.
TheDeepestSpace
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Mar 9, 2026
| @@ -0,0 +1,63 @@ | |||
| `timescale 1ns / 1ps | |||
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Probably better to move all uart-related modules into src/uart/. I think eventually we will try to keep the peripherals in a separate repo entirely, but its fine for now.
add some fixes to the simulation and de1-soc env
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TheDeepestSpace
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May 26, 2026
| , output logic [3:0] bus_write_enable | ||
| , input wire [31:0] bus_read_data | ||
| , output logic hold_core | ||
| // , input logic [31:0] dbg_regs [0:31] |
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The fanout from these was pretty drastic downstream; @RunzeZhu28 if you get a chance to take a look at how we can optimize this would be sick
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New version of #148