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arm64:dts:xilinx:Add AD9084 M4_L12_NP12_20p0_4x1 - #3594
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chegbeli
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amiclaus,
btogorean,
buha,
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stefpopa
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October 9, 2026 10:33
Add REV A and REV B device tree overlays for the AD9084 VPX carrier together with the 204C_M4_L12_NP12_20p0_4x1 device profile. The profile runs the JESD204C links with L=12, M=4, N=NP=12, subclass 0 at a 20.625 Gbps lane rate and a 20 GHz device clock. Signed-off-by: Filip Gherman <filip.gherman@analog.com> Signed-off-by: Ciprian Hegbeli <ciprian.hegbeli@analog.com>
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gastmaier
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Oct 12, 2026
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PR Description
The profile runs the JESD204C links with L=12, M=4, N=NP=12, subclass 0 at a
20.625 Gbps lane rate and a 20 GHz device clock. The profile be used on any
AD9084 boards.
No dependencies on other repos; no existing overlay or profile is modified.
PR Type
PR Checklist