feat(plat): add Agilex5 support

[rabara]

Add support for the Altera Agilex 5 SoC FPGA (HPS: 2x Cortex-A76 + 2x Cortex-A55), covering the GICv3, DDR memory map (sized via AGX5_MEM_GB), 8250 UART console and generic timer.

Depends on #338

[josecm]

Hey @rabara! Very exciting to see a new platform from a vendor we haven't worked with! Thank you for this contribution.

If you have the bandwidth please consider also submitting a demo (ideally linux+freertos, but purely the baremetal would suffice) so people can easily try out this platform.

[rabara]

Hey @rabara! Very exciting to see a new platform from a vendor we haven't worked with! Thank you for this contribution.

If you have the bandwidth please consider also submitting a demo (ideally linux+freertos, but purely the baremetal would suffice) so people can easily try out this platform.

Hi @josecm
Thanks! Yes, I'll add a bare-metal demo as a starting point.

I already have Linux + FreeRTOS working locally and plan to contribute it to bao-demos later. There are a few fixes and code changes needed in Bao (mainly around GICv3 and cache coloring). I'll submit those as separate PRs so they can be reviewed independently.

I'm also currently using a different SMMUv3 implementation. I noticed there's already a draft PR for SMMUv3, so I'll share my implementation as well.

[josecm]

There are a few fixes and code changes needed in Bao (mainly around GICv3 and cache coloring). I'll submit those as separate PRs so they can be reviewed independently.

This sounds great @rabara! Really looking forward for these contributions!

I'm also currently using a different SMMUv3 implementation. I noticed there's already a draft PR for SMMUv3, so I'll share my implementation as well.

We are also starting to look finally pushing forward that PR as some of the platforms in our roadmap feature one. So we can wait for this PR and then give feedback on it based on our current work also and test it on our side. @joaopeixoto13 can follow up with you when you submit that PR

[rabara]

We are also starting to look finally pushing forward that PR as some of the platforms in our roadmap feature one. So we can wait for this PR and then give feedback on it based on our current work also and test it on our side. @joaopeixoto13 can follow up with you when you submit that PR

SMMUv3 PR - #382

[joaopeixoto13]

Hi @rabara

I just noticed that the Altera Agilex 5 SoC FPGA features 2× Cortex-A76 + 2× Cortex-A55. Out of curiosity, did you use this PR when validating this platform?

I'm asking because newer Arm CPU topologies (e.g. Cortex-A55, Cortex-A76, Cortex-A78AE) no longer encode the CPU ID in Aff0 (MPIDR_EL1[7:0]), but in Aff1 (MPIDR_EL1[15:8]).

[rabara]

Hi @rabara

I just noticed that the Altera Agilex 5 SoC FPGA features 2× Cortex-A76 + 2× Cortex-A55. Out of curiosity, did you use this PR when validating this platform?

I'm asking because newer Arm CPU topologies (e.g. Cortex-A55, Cortex-A76, Cortex-A78AE) no longer encode the CPU ID in Aff0 (MPIDR_EL1[7:0]), but in Aff1 (MPIDR_EL1[15:8]).

Hi @joaopeixoto13

No I didn't try this #338
You are right CPU ID is in Aff1, Agilex5 CPU ID in Aff1 is as below.

Currently I model it as .clusters = { .num = 4, .core_num = {1,1,1,1} }, which yields the same 0x0/0x100/0x200/0x300 and works standalone.

Your point is with #338 , Agilex5 can use cleaner single-cluster form (.num = 1, .core_num = {4}) ?

[joaopeixoto13]

Hi @rabara
I just noticed that the Altera Agilex 5 SoC FPGA features 2× Cortex-A76 + 2× Cortex-A55. Out of curiosity, did you use this PR when validating this platform?
I'm asking because newer Arm CPU topologies (e.g. Cortex-A55, Cortex-A76, Cortex-A78AE) no longer encode the CPU ID in Aff0 (MPIDR_EL1[7:0]), but in Aff1 (MPIDR_EL1[15:8]).

Hi @joaopeixoto13

No I didn't try this #338 You are right CPU ID is in Aff1, Agilex5 CPU ID in Aff1 is as below.

Currently I model it as .clusters = { .num = 4, .core_num = {1,1,1,1} }, which yields the same 0x0/0x100/0x200/0x300 and works standalone.
Your point is with #338 , Agilex5 can use cleaner single-cluster form (.num = 1, .core_num = {4}) ?

Yes, exactly. Since we're planning to merge that PR, could you please test your setup with it and let me know whether everything runs correctly?

[rabara]

Hi @joaopeixoto13

I have tested #338 and its working on my side.
I have updated my PR to use .clusters = { .num = 1, .core_num = (size_t[]){ 4 }, },

[joaopeixoto13]

Hi @joaopeixoto13

I have tested #338 and its working on my side. I have updated my PR to use .clusters = { .num = 1, .core_num = (size_t[]){ 4 }, },

Great! Thanks for confirming that everything is working.

[josecm]

Let's first push the merge on #338 before going ahead with this one!

[josecm]

@joaopeixoto13 good to go for me if it is with you!

[joaopeixoto13]

@joaopeixoto13 good to go for me if it is with you!

Yeah, everything looks good to me as well.