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cmd/compile: use memory operands in amd64 carry chains #82122

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8 changes: 8 additions & 0 deletions src/cmd/compile/internal/amd64/ssa.go
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Original file line number Diff line number Diff line change
Expand Up @@ -564,6 +564,14 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
p.To.Type = obj.TYPE_REG
p.To.Reg = v.Reg0()

case ssaop.OpAMD64ADDQcarryload, ssaop.OpAMD64ADCQload, ssaop.OpAMD64SUBQborrowload, ssaop.OpAMD64SBBQload:
p := s.Prog(v.Op.Asm())
p.From.Type = obj.TYPE_MEM
p.From.Reg = v.Args[1].Reg()
ssagen.AddAux(&p.From, v)
p.To.Type = obj.TYPE_REG
p.To.Reg = v.Reg0()

case ssaop.OpAMD64ADDQconstcarry, ssaop.OpAMD64ADCQconst, ssaop.OpAMD64SUBQconstborrow, ssaop.OpAMD64SBBQconst:
p := s.Prog(v.Op.Asm())
p.From.Type = obj.TYPE_CONST
Expand Down
19 changes: 19 additions & 0 deletions src/cmd/compile/internal/ssa/_gen/AMD64.rules
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Expand Up @@ -48,6 +48,15 @@
(ADCQconst x [c] (InvertFlags f)) => (ADCQconst x [c] (Select1 <types.TypeFlags> (NEGLflags (MOVBQZX <types.Types[types.TUINT32]> (SETA <types.Types[types.TUINT8]> f)))))
(SBBQ x y (InvertFlags f)) => (SBBQ x y (Select1 <types.TypeFlags> (NEGLflags (MOVBQZX <types.Types[types.TUINT32]> (SETA <types.Types[types.TUINT8]> f)))))
(SBBQconst x [c] (InvertFlags f)) => (SBBQconst x [c] (Select1 <types.TypeFlags> (NEGLflags (MOVBQZX <types.Types[types.TUINT32]> (SETA <types.Types[types.TUINT8]> f)))))
(ADCQload x [off] {sym} ptr (InvertFlags f) mem) => (ADCQload x [off] {sym} ptr (Select1 <types.TypeFlags> (NEGLflags (MOVBQZX <types.Types[types.TUINT32]> (SETA <types.Types[types.TUINT8]> f)))) mem)
(SBBQload x [off] {sym} ptr (InvertFlags f) mem) => (SBBQload x [off] {sym} ptr (Select1 <types.TypeFlags> (NEGLflags (MOVBQZX <types.Types[types.TUINT32]> (SETA <types.Types[types.TUINT8]> f)))) mem)
// Merge a load into the second operand of ADCQ and friends.
(ADDQcarry x l:(MOVQload [off] {sym} ptr mem)) && ssa.CanMergeLoadClobber(v, l, x) && ssa.Clobber(l) => (ADDQcarryload x [off] {sym} ptr mem)
(ADCQ x l:(MOVQload [off] {sym} ptr mem) carry) && ssa.CanMergeLoadClobber(v, l, x) && ssa.Clobber(l) => (ADCQload x [off] {sym} ptr carry mem)
(SUBQborrow x l:(MOVQload [off] {sym} ptr mem)) && ssa.CanMergeLoadClobber(v, l, x) && ssa.Clobber(l) => (SUBQborrowload x [off] {sym} ptr mem)
(SBBQ x l:(MOVQload [off] {sym} ptr mem) borrow) && ssa.CanMergeLoadClobber(v, l, x) && ssa.Clobber(l) => (SBBQload x [off] {sym} ptr borrow mem)
(ADCQload x [off] {sym} ptr (FlagEQ) mem) => (ADDQcarryload x [off] {sym} ptr mem)
(SBBQload x [off] {sym} ptr (FlagEQ) mem) => (SUBQborrowload x [off] {sym} ptr mem)
// ADDQ/SUBQ an from a carry flag into ADCQ/SBBQ
// TODO: maybe add ADCL and SBBL ?
(ADDQ x (MOVBQZX (SETB flags))) => (Select0 (ADCQconst [0] x flags))
Expand Down Expand Up @@ -1030,6 +1039,10 @@
((ADD|SUB|AND|OR|XOR)Qload [off1+off2] {sym} val base mem)
((ADD|SUB|AND|OR|XOR)Lload [off1] {sym} val (ADDQconst [off2] base) mem) && ssa.Is32Bit(int64(off1)+int64(off2)) =>
((ADD|SUB|AND|OR|XOR)Lload [off1+off2] {sym} val base mem)
((ADDQcarry|SUBQborrow)load [off1] {sym} val (ADDQconst [off2] base) mem) && ssa.Is32Bit(int64(off1)+int64(off2)) =>
((ADDQcarry|SUBQborrow)load [off1+off2] {sym} val base mem)
((ADC|SBB)Qload [off1] {sym} val (ADDQconst [off2] base) carry mem) && ssa.Is32Bit(int64(off1)+int64(off2)) =>
((ADC|SBB)Qload [off1+off2] {sym} val base carry mem)
(CMP(Q|L|W|B)load [off1] {sym} (ADDQconst [off2] base) val mem) && ssa.Is32Bit(int64(off1)+int64(off2)) =>
(CMP(Q|L|W|B)load [off1+off2] {sym} base val mem)
(CMP(Q|L|W|B)constload [valoff1] {sym} (ADDQconst [off2] base) mem) && ssa.ValAndOff(valoff1).CanAdd32(off2) =>
Expand Down Expand Up @@ -1085,6 +1098,12 @@
((ADD|SUB|AND|OR|XOR)Lload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
&& ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) =>
((ADD|SUB|AND|OR|XOR)Lload [off1+off2] {ssa.MergeSym(sym1,sym2)} val base mem)
((ADDQcarry|SUBQborrow)load [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
&& ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) =>
((ADDQcarry|SUBQborrow)load [off1+off2] {ssa.MergeSym(sym1,sym2)} val base mem)
((ADC|SBB)Qload [off1] {sym1} val (LEAQ [off2] {sym2} base) carry mem)
&& ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) =>
((ADC|SBB)Qload [off1+off2] {ssa.MergeSym(sym1,sym2)} val base carry mem)
(CMP(Q|L|W|B)load [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
&& ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) =>
(CMP(Q|L|W|B)load [off1+off2] {ssa.MergeSym(sym1,sym2)} base val mem)
Expand Down
10 changes: 10 additions & 0 deletions src/cmd/compile/internal/ssa/_gen/AMD64Ops.go
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Expand Up @@ -165,6 +165,9 @@ func init() {
gp21flags = regInfo{inputs: []regMask{gp, gp}, outputs: []regMask{gp, regMask{}}}
gp2flags1flags = regInfo{inputs: []regMask{gp, gp, regMask{}}, outputs: []regMask{gp, regMask{}}}

gp21loadflags = regInfo{inputs: []regMask{gp, gpspsbg, regMask{}}, outputs: []regMask{gp, regMask{}}}
gp2flags1loadflags = regInfo{inputs: []regMask{gp, gpspsbg, regMask{}, regMask{}}, outputs: []regMask{gp, regMask{}}}

gp2flags = regInfo{inputs: []regMask{gpsp, gpsp}}
gp1flags = regInfo{inputs: []regMask{gpsp}}
gp0flagsLoad = regInfo{inputs: []regMask{gpspsbg, regMask{}}}
Expand Down Expand Up @@ -429,6 +432,13 @@ func init() {
{name: "SUBQconstborrow", argLength: 1, reg: gp11flags, typ: "(UInt64,Flags)", asm: "SUBQ", aux: "Int32", resultInArg0: true}, // r = arg0-auxint
{name: "SBBQconst", argLength: 2, reg: gp1flags1flags, typ: "(UInt64,Flags)", asm: "SBBQ", aux: "Int32", resultInArg0: true}, // r = arg0-(auxint+carry(arg1))

// Load/op combos of the carry and borrow ops above, with the second operand
// read from memory. The memory argument comes last.
{name: "ADDQcarryload", argLength: 3, reg: gp21loadflags, typ: "(UInt64,Flags)", asm: "ADDQ", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read", addrSinkArg1: true}, // r = arg0+*(arg1+auxint+aux), arg2=mem
{name: "ADCQload", argLength: 4, reg: gp2flags1loadflags, typ: "(UInt64,Flags)", asm: "ADCQ", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read", addrSinkArg1: true}, // r = arg0+*(arg1+auxint+aux)+carry(arg2), arg3=mem
{name: "SUBQborrowload", argLength: 3, reg: gp21loadflags, typ: "(UInt64,Flags)", asm: "SUBQ", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read", addrSinkArg1: true}, // r = arg0-*(arg1+auxint+aux), arg2=mem
{name: "SBBQload", argLength: 4, reg: gp2flags1loadflags, typ: "(UInt64,Flags)", asm: "SBBQ", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read", addrSinkArg1: true}, // r = arg0-(*(arg1+auxint+aux)+carry(arg2)), arg3=mem

{name: "MULQU2", argLength: 2, reg: regInfo{inputs: []regMask{ax, gpsp}, outputs: []regMask{dx, ax}}, commutative: true, asm: "MULQ", clobberFlags: true, earlyOk: true}, // arg0 * arg1, returns (hi, lo)
// MULXQ is the BMI2 unsigned 64x64->128 multiply. arg0 must be in DX
// (the implicit operand); arg1 is any register or memory. Outputs are
Expand Down
7 changes: 7 additions & 0 deletions src/cmd/compile/internal/ssa/_gen/AMD64splitload.rules
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Expand Up @@ -43,3 +43,10 @@
(CMPQconstloadidx8 {sym} [vo] ptr idx mem) && vo.Val() != 0 => (CMPQconst (MOVQloadidx8 {sym} [vo.Off()] ptr idx mem) [vo.Val()])
(CMPLconstloadidx4 {sym} [vo] ptr idx mem) && vo.Val() != 0 => (CMPLconst (MOVLloadidx4 {sym} [vo.Off()] ptr idx mem) [vo.Val()])
(CMPWconstloadidx2 {sym} [vo] ptr idx mem) && vo.Val() != 0 => (CMPWconst (MOVWloadidx2 {sym} [vo.Off()] ptr idx mem) [vo.Val16()])

// Load/op combos of the carry chain ops. These are tuple-valued, so flagalloc
// splits them when it needs to recompute their flags result elsewhere.
(ADDQcarryload {sym} [off] x ptr mem) => (ADDQcarry x (MOVQload <x.Type> {sym} [off] ptr mem))
(ADCQload {sym} [off] x ptr carry mem) => (ADCQ x (MOVQload <x.Type> {sym} [off] ptr mem) carry)
(SUBQborrowload {sym} [off] x ptr mem) => (SUBQborrow x (MOVQload <x.Type> {sym} [off] ptr mem))
(SBBQload {sym} [off] x ptr borrow mem) => (SBBQ x (MOVQload <x.Type> {sym} [off] ptr mem) borrow)
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