Push 2026 07 08.1 - #1038
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Change-Id: I01ca652ab0f759e3caa01c4ece74f6a362d8c97a
Change-Id: If4b29ac7d229fd5a1a638c3b4c60fe53c0217519
Co-authored-by: Copilot Autofix powered by AI <175728472+Copilot@users.noreply.github.com>
Co-authored-by: Copilot Autofix powered by AI <175728472+Copilot@users.noreply.github.com>
* Consolidate sensor server docs into PCM exporter guide * Update PCM-EXPORTER.md * Fix PCM exporter metric descriptions per review --------- Co-authored-by: copilot-swe-agent[bot] <198982749+Copilot@users.noreply.github.com> Co-authored-by: Roman Dementiev <roman.dementiev@intel.com>
Change-Id: I5d7edbcad48b0c3135f5e4e58c808633dfc75599 Co-authored-by: Alexander Antonov <alexander.antonov@intel.com> Co-authored-by: Roman Dementiev <roman.dementiev@intel.com>
…example files (#951) --------- Co-authored-by: copilot-swe-agent[bot] <198982749+Copilot@users.noreply.github.com> Co-authored-by: Roman Dementiev <roman.dementiev@intel.com>
--------- Co-authored-by: Copilot Autofix powered by AI <175728472+Copilot@users.noreply.github.com>
Add new tool pcm-io
Change-Id: If72c38472bd7f2618138ecddc72d99ef9b7a4306
Add official perfmon event names (from perfmon/{ICX,SPR,EMR,SKX,CLX}/events/*_uncore.json)
as comments next to the hard-coded iMC uncore event codes in
programServerUncoreLatencyMetrics.
Change-Id: I97c56087236b7909a0423b0500744899ff8ffacd
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
These CPUs use a different iMC uncore layout (SCH0/SCH1 sub-channels,
PCH0/PCH1 pseudo-channels) with WPQ occupancy/inserts on new event codes
(0x84/0x22). Add a dedicated DDR branch using the SCH0_PCH0 variants and
enable DDRLatencyMetricsAvailable() for these models. Event codes verified
against perfmon/{GNR,SRF,CWF}/events/*_uncore.json.
Change-Id: I9ef5366c2f640e1cbf7b06d28acec40242749e84
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Replace the if/else if/else chain in programServerUncoreLatencyMetrics with a switch on cpu_family_model. No behavior change. Change-Id: I69673f7c17fb2157bc795043cc5053ddaa6db21a Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Name the core PMU event/umask encodings used for the L1 fill-buffer latency metric in build_core_register. Express the inserts umask as FB_HIT | L1_MISS instead of a precomputed 0x48. Encodings verified against the perfmon core JSONs (valid on P-core parts; E-core SRF/CWF lack these events and remain excluded from LatencyMetricsAvailable). Change-Id: I5cacad6b58375ccffb4828947a79f532da30cb90 Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Add GNR/GNR-D to LatencyMetricsAvailable now that their P-core L1D_PEND_MISS / MEM_LOAD_RETIRED encodings are confirmed to match the ones used in pcm-latency. E-core SRF/CWF stay excluded (they lack the fill-buffer-occupancy event and use different umasks). Change-Id: I1e208fce34ff009211ca16712795c6d5f7a2bf33 Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Decouple the core L1 fill-buffer latency path from the DDR uncore latency path in pcm-latency. The platform gate now permits parts that support only DDR latency, and core-event programming, collection, and printing are skipped when LatencyMetricsAvailable() is false. On such parts (e.g. the E-core SRF/CWF) the tool now reports DDR read/write latency instead of aborting with "Platform not Supported". P-core behavior is unchanged. Change-Id: I5e282202b897b1bddff9bfd1d5e24bc6bef3fd40 Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
DDRConfig[2] used event 0x81 (UNC_M_RPQ_OCCUPANCY_PCH1, a read queue)
while labeled "WPQ Occupancy". The write-queue occupancy on ICX/SPR/EMR
is event 0x82 (UNC_M_WPQ_OCCUPANCY_PCH0). Also set the WPQ insert umask
to PCH0 so both write counters cover the same pseudo-channel as the read
pair, making the write-latency occupancy/inserts ratio meaningful.
Verified against perfmon/{ICX,SPR,EMR}/events/*_uncore.json.
Change-Id: Ib1f4fec9c83caa4c47561be88cb98e126e4bd4dc
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
…ming errors, reword perfmon path comments
…port Remove macOS/OSX support and the MacMSRDriver
Change-Id: Ie645a74efe859486be17bfa52ed28fca8505620e
--------- Co-authored-by: copilot-swe-agent[bot] <198982749+Copilot@users.noreply.github.com>
Change-Id: I20a016b89600b7c0b904c55d94d5096255f12d23
opcm
approved these changes
Jul 8, 2026
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