Netlist synthesizer#654
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Note that I moved examples into lib/src to enable them to be used as part of tests. The example directory has the outer main and tests for these examples. |
…al/instance naming routine names
Introduces a singleton service registry (ModuleServices) that provides a unified query surface for DevTools and inspection tools. Module.build() now registers the root module with ModuleServices.instance. Also adds SvService which wraps SystemVerilog synthesis and registers with ModuleServices for DevTools access to SV metadata. This is a clean separation: no netlist code is included. The netlist branch will later extend ModuleServices with a netlistService field.
Adds a complete netlist synthesis pipeline that converts ROHD module hierarchies into Yosys-compatible JSON netlists. Key additions: - NetlistSynthesizer: traverses module hierarchy producing cell/wire JSON - NetlistService: async factory that registers with ModuleServices - NetlistOptions: configurable post-processing passes (DCE, struct grouping, concat collapsing, etc.) - NetlistPasses: optimization and structural transformations - LeafCellMapper: maps ROHD gates to standard cell definitions - NetlistUtils: wire naming, bit-range formatting, JSON helpers Also extends Module.build() with optional netlistOptions parameter, updates ModuleServices with netlistService field, and refactors examples into lib/src/examples/ for reuse in tests. Comprehensive test coverage across 11 new/updated test files (146 tests).
Introduces a singleton service registry (ModuleServices) that provides a unified query surface for DevTools and inspection tools. Module.build() now registers the root module with ModuleServices.instance. Also adds SvService which wraps SystemVerilog synthesis and registers with ModuleServices for DevTools access to SV metadata. This is a clean separation: no netlist code is included. The netlist branch will later extend ModuleServices with a netlistService field.
Adds a complete netlist synthesis pipeline that converts ROHD module hierarchies into Yosys-compatible JSON netlists. Key additions: - NetlistSynthesizer: traverses module hierarchy producing cell/wire JSON - NetlistService: async factory that registers with ModuleServices - NetlistOptions: configurable post-processing passes (DCE, struct grouping, concat collapsing, etc.) - NetlistPasses: optimization and structural transformations - LeafCellMapper: maps ROHD gates to standard cell definitions - NetlistUtils: wire naming, bit-range formatting, JSON helpers Also extends Module.build() with optional netlistOptions parameter, updates ModuleServices with netlistService field, and refactors examples into lib/src/examples/ for reuse in tests. Comprehensive test coverage across 11 new/updated test files (146 tests).
Remove unnecessary Simulator.reset() from module_services_test tearDown since no tests in this file use the Simulator. This aligns with the module_services and devtool_utilities branches to eliminate merge conflicts.
…ggressive tearoff that dropped Simulator.reset)
…n, and port-skip in swizzle collapsing - Remove orphaned netnames after DCE (Group A): prevents dead signals from appearing in the schematic viewer when their driving cells are eliminated. - Add _validateNetlist debug-mode assertion (Group B): checks for fully disconnected logic gates and floating $const cells under --enable-asserts. - Skip swizzle output collapsing when members are module ports (Group D): prevents orphaning module-level port bits during output aggregation.
… named-const test - Fix multi-dimensional LogicArray exclusion: exclude nested sub-arrays from spurious $concat cell generation (prevents multi-driver conflicts) - Break shared wire IDs for array_slice output ports so structural decomposition is preserved in schematic - Add DCE formatting fixes (curly-brace continue style) - Extend netlist_utils.dart: LogicArray metadata (arrayDims, elementWidth, nested struct/array elementType) in buildLogicType - Add Group 11 test: Logic..gets(Const) named-constant $const cell
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Description & Motivation
This is a netlist synthesizer that uses central naming to match the names of our SystemVerilog synthesizer but outputs in the Yosys JSON format for external use.
Also added are examples, pushed into lib/src so that we can access them with tests.
One exhaustive example is filter_bank which has all elements of ROHD included.
Related Issue(s)
This PR includes all changes from PR #652, so we should merge that first to be clean.
Testing
Netlist tests are included using the examples.
Backwards-compatibility
No.
Documentation
Yes, it is a new capability. Basic documentation is in
architecture.mdand in one of the tutorials.