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Removed hard coded values for hs-64 voltage #147

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Merged
cjsha merged 3 commits into from
May 12, 2026
Merged

Removed hard coded values for hs-64 voltage #147

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f85660c
Removed hard coded values for hs-64 voltage
ChucklesOnGitHub Mar 17, 2026
50160b3
small edit
cjsha May 12, 2026
e0be8fe
Merge branch 'main' into patch-1
cjsha May 12, 2026
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2 changes: 1 addition & 1 deletion source/Hardware Guide/Headstages/tether-voltage.rst
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Expand Up @@ -14,7 +14,7 @@ Setting Headstage Voltage
--------------------------
The headstage voltage is set using :ref:`onidatasheet_fmc_link_control` devices
on the :ref:`pcie_controller`. Each headstage has a minimum and maximum voltage
requirement (e.g. 5.3 to 5.7 Volts for :ref:`headstage_64`) in order for
requirement listed under the Data Link Serialization/Coaxial Link section on its own hardware page (e.g. :ref:`headstage_64`) in order for
circuits on the board to function properly. If the voltage is far too low, the
host computer will not be able to detect the headstage. A borderline
voltage can still cause connectivity issues as the headstage occasionally dips
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