DNM: do-not-merge: remoteproc: qcom_q6v5: panic on watchdog/fatal if dump_conf not set#591
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The Shikra SoM is a compact compute module integrating the SoC and essential components optimized for IoT applications, designed to mount on carrier boards. Shikra supports three SoM variants: two retail options (with and without modem) and one industrial variant , represented by the following device trees: - shikra-cqm-som.dtsi : Retail SoM with modem - shikra-cqs-som.dtsi : Retail SoM without modem - shikra-iqs-som.dtsi : Industrial SoM without modem Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Add device trees for the Shikra EVK platform, which combines Shikra SoM with a common carrier board. Introduce DTS files for CQM, CQS and IQS EVK variants: - shikra-cqm-evk.dts - shikra-cqs-evk.dts - shikra-iqs-evk.dts Also add a shared include file, shikra-evk.dtsi, which contains the common daughter card nodes used across Shikra EVK variants. Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Add the reserved memory nodes for Shikra. Signed-off-by: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
Add the apps and adreno smmu node as found in Shikra SoC. Signed-off-by: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
Add qcom,shikra-apcs-hmss-global for the APCS mailbox binding. This avoids undocumented-compatible warnings from checkpatch and keeps schema constraints aligned for this target. Signed-off-by: Vishnu Santhosh <vishnu.santhosh@oss.qualcomm.com>
Add the RPM message RAM SRAM region and APCS HMSS global mailbox controller, and wire them up to a new glink-edge node. The rpm_msg_ram node exposes the shared SRAM used for GLINK FIFOs and includes the apss_mpm sub-node for the MPM sleep counter. The `qcom,glink-rpm` transport uses: - `qcom,rpm-msg-ram` for shared GLINK FIFOs - APCS mailbox channel 0 for kick/notify This enables RPM GLINK-based inter-processor communication on Shikra. Signed-off-by: Vishnu Santhosh <vishnu.santhosh@oss.qualcomm.com>
Add qfprom node and its properties for Shikra SoC. Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Move rpm_requests node to under glink-edge node. Signed-off-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com>
Add support for RPMCC and GCC nodes on Shikra platforms. Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
Add spmi-pmic-arb device for the SPMI PMIC arbiter found on shikra. Signed-off-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com>
Add the RPM SMD power domain controller node for Shikra with a complete OPP table covering all 8 voltage corners from MIN_SVS to TURBO_NO_CPR. Signed-off-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com>
Add RPM regulator for the Shikra Retail (CQM/CQS) SOM variants using pm4125-regulators with S1-S4 buck switchers and L1-L22 LDOs, and for the Industrial (IQS) SOM variant using pm8150-regulators with S4-S9 buck switchers and L1-L18 LDOs. Signed-off-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com>
Add the watchdog node for Shikra SoC. Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Describe the TCSR mutex hwlock controller and reference it from the SMEM node to enable proper hardware locking on Shikra. Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Add interconnect devices for config_noc, system_noc, mc_virt, clk_virt, mem_noc, mmnrt_virt and mmrt_virt. This will allow consumers to get their path and set bandwidth constraints on them. Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
Add the SCM firmware node and TCSR syscon required to support download mode on Shikra. Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Enable console support for shikra. Signed-off-by: Xueyao An <xueyao.an@oss.qualcomm.com>
Add support for eMMC on shikra SoC and enable the required pinctrl configurations. Signed-off-by: Monish Chunara <quic_mchunara@quicinc.com>
Enable eMMC for shikra CQS, CQM and IQS EVK variants. Signed-off-by: Monish Chunara <quic_mchunara@quicinc.com>
Add support for SD card on shikra SoC and enable the required pinctrl configurations. Signed-off-by: Monish Chunara <quic_mchunara@quicinc.com>
Add usb related changes on Shikra specifically: a) Primary controller node b) Primary high speed phy c) QMP Phy for super speed operation Enable USB controller and phys in device mode on CQS and CQM variants. Add the regulators for the phys accordingly. Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
Add cpufreq-hw node to support cpufreq scaling on Qualcomm Shikra SoCs. Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
Add SMP2P nodes for the cdsp, modem and lmcu subsystems to enable inter-processor signalling for remoteproc state management. Signed-off-by: Vishnu Santhosh <vishnu.santhosh@oss.qualcomm.com>
Enable primary usb controller on IQS platform in peripheral mode. Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
The shikra includes one TSENS instance, with a total of 14 thermal sensors distributed across various locations on the SoC. The TSENS max/reset threshold is configured to 120°C in the hardware. Enable all TSENS instances, and define the thermal zones with a hot trip at 110°C and critical trip at 115°C. Signed-off-by: Gaurav Kohli <gaurav.kohli@oss.qualcomm.com>
Traditionally, firmware loading for Serial Engines (SE) in the QUP hardware of Qualcomm SoCs has been managed by TrustZone (TZ). While this approach ensures secure SE assignment and access control, it limits flexibility for developers who need to enable various protocols on different SEs. Add the firmware-name property to QUPv3 nodes in the device tree to enable firmware loading from the Linux environment. Handle SE assignments and access control permissions directly within Linux, removing the dependency on TrustZone. Signed-off-by: Xueyao An <xueyao.an@oss.qualcomm.com>
Add PMIC topic overlay changes for Shikra SOM variants (CQM, CQS, IQS): - Add pm4125 temp-alarm and VADC channel nodes - Add pm8005 temp-alarm node - Add thermal zones for PMIC and system thermistors - Add GPIO key (volume up) bindings - Add ADC thermal bridge nodes for pa/quiet/msm thermistors - Disable pm8005 regulators across SOM variants - Switch SPMI interrupt to MPM edge-triggered Signed-off-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com>
Add support for DISPCC and GPUCC nodes on Qualcomm Shikra platforms. Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
Add clock entries for adreno smmu node in Shikra. Signed-off-by: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
Introduce the WiFi hardware description in shikra.dtsi, including register space, interrupts, IOMMU configuration and reserved memory. The node is kept disabled by default and is intended to be enabled by board-specific device trees. Signed-off-by: Miaoqing Pan <miaoqing.pan@oss.qualcomm.com>
QCM2290 is currently supported by the Venus driver using HFI Gen1. However, support for this platform is being added to the Iris driver, where it will be preferred going forward, initially using HFI Gen2 and eventually providing support for both Gen1 and Gen2. As part of early enablement for the Shikra platform, which reuses the qcm2290 compatible as a fallback, it is necessary to allow the Iris driver to bind to this hardware instead of Venus when Iris support is enabled in the kernel configuration. Introduce a configuration-based guard to prevent the Venus driver from registering qcm2290 support when CONFIG_VIDEO_QCOM_IRIS is enabled. This ensures that the Iris driver is selected for QCM2290/Shikra platforms in early development kernels, without changing the default behavior when Iris is not enabled. This change is intended as an intermediate step for early bring-up. Full HFI Gen1 support in the Iris driver will be added before posting the final upstream series. Signed-off-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
…ap_attach() Commit c7d8100 introduced a brace-less if that skips the dma_buf_map_attachment_unlocked() call when sess->coherent is true, leaving 'table' uninitialized. The unconditional IS_ERR(table) check that follows does not catch NULL, so execution continues with a NULL sg_table, causing a level-0 translation fault when the sgl pointer is dereferenced. Remove the guard; the mapping is always needed to obtain DMA addresses consumed by the rest of the function. Signed-off-by: Anandu Krishnan E <anandu.e@oss.qualcomm.com>
Add qcrypto and cryptobam support for shikra target. Link: https://lore.kernel.org/lkml/20260515-shikra_qcrypto-v1-3-80f07b345c29@oss.qualcomm.com/ Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
Add True Random Number Generator(TRNG) node for shikra. Link: https://lore.kernel.org/lkml/20260514-shikra_rng-v1-2-4ea721a1429a@oss.qualcomm.com/ Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
Add UFS inline crypto engine(ICE) support for shikra. Link: https://lore.kernel.org/lkml/20260515-shikra_ice_ufs-v1-2-b1b6ced70559@oss.qualcomm.com Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
Add pm4125_s1 regulator node at fixed 1.396V to both shikra-cqm-som and shikra-cqs-som. This rail is used by the audio subsystem. Signed-off-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com>
…-reg The pm4125 PMIC uses a different USB VBUS register layout than pm8150b. It uses a 2-bit VBOOST voltage selector supporting output voltages of 4.25 V, 4.5 V, 4.75 V and 5.0 V, instead of a current-limit selector. Move qcom,pm4125-vbus-reg from the pm8150b fallback items list into the standalone enum since the driver handles it with its own match-data and register layout. Make regulator-min/max-microamp conditional so they are only required for current-limit variants (pm8150b, pm6150, pm7250b, pmi632). Add an if/then condition for qcom,pm4125-vbus-reg requiring regulator-min/ max-microvolt instead, and update the pm4125 example accordingly. Signed-off-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com>
The PM4125 PMIC uses a different register layout for USB VBUS control compared to PM8150B. On PM4125, CMD_OTG is at offset 0x50, OTG_CFG is at 0x56, and offset 0x52 is a 2-bit VBOOST voltage selector rather than a current-limit selector. Introduce per-compatible regulator descriptor data to accommodate these differences. This keeps the existing PM8150B current-limit logic intact while adding a dedicated voltage-selector path for PM4125. Signed-off-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com>
Document shikra compatible for the True Random Number Generator. Link: https://lore.kernel.org/lkml/20260514-shikra_rng-v1-1-4ea721a1429a@oss.qualcomm.com/ Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
…ngine Document the crypto engine on the Shikra platform. Link:https://lore.kernel.org/lkml/20260515-shikra_qcrypto-v1-1-80f07b345c29@oss.qualcomm.com/ Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
Shikra bam dma engine support seven iommu entries. Increase maxItems property for iommus to pass dtbs_check errors. Link: https://lore.kernel.org/lkml/20260515-shikra_qcrypto-v1-2-80f07b345c29@oss.qualcomm.com/ Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
Document the Inline Crypto Engine (ICE) on the Shikra platform. Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
…sent Some clock controller descriptors do not provide any reset lines. Avoid registering a reset controller when desc->num_resets is zero by making the registration conditional. Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
Some Qualcomm clock controller descriptors may contain NULL entries in the clk_hws array. Skip such entries when registering clock hardware to avoid passing NULL pointers to the clock framework. Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
Add GCC LPASS clocks support for Qualcomm Shikra SoC. Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
The GCC LPASS clocks must be enabled to access audio core clock controller registers. Hence, mark them as critical on Qualcomm Shikra SoCs. Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
…ller Add device tree bindings for the Audio Core clock controller on Qualcomm Shikra SoC. Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
… SoC Add support for Audio core clock controller on Qualcomm Shikra SoC. Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
Add a separate fixed dummy regulator for Bluetooth. Signed-off-by: Yepuri Siddu <yepuri.siddu@oss.qualcomm.com>
Enable the DLC0697 MIPI DSI display panel on the Shikra CQS EVK. Signed-off-by: Mahadevan P <mahadevan.p@oss.qualcomm.com>
Shikra shares the same power domain topology as sm6125. Remove the dedicated shikra_rpmpds[] and update shikra_desc to reuse sm6125_rpmpds[] with RPM_SMD_LEVEL_TURBO_NO_CPR. Signed-off-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com>
If the remoteproc dump_conf is not configured, trigger a SoC reset via panic() on both watchdog and fatal error interrupts before reporting the crash. This ensures the system resets cleanly when coredump collection is not enabled. Signed-off-by: Anurag Pateriya <apateriy@qti.qualcomm.com>
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If the remoteproc dump_conf is not configured, trigger a SoC reset via panic() on both watchdog and fatal error interrupts before reporting the crash. This ensures the system resets cleanly when coredump collection is not enabled.