standardsemiconductor · felipebalbi · Aug 2, 2026 · Aug 2, 2026
diff --git a/.github/workflows/haskell.yml b/.github/workflows/haskell.yml
@@ -14,7 +14,7 @@ jobs:
     runs-on: ${{ matrix.os }} 
     strategy:
       matrix:
-        ghc: ['9.0', '9.4', '9.6']
+        ghc: ['9.0', '9.4', '9.6', '9.8', '9.10']
         os: [ubuntu-20.04]
 
     name: ${{ matrix.os }} GHC ${{ matrix.ghc }}

diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -1,5 +1,14 @@
 # Revision history for ice40-prim
 
+## Unreleased
+* Mark primitives `OPAQUE` rather than `NOINLINE` on GHC >= 9.4. Clash 1.10
+  warns that a primitive marked `NOINLINE` "might make Clash ignore this
+  primitive". Guarded by CPP, so GHC 9.0 keeps `NOINLINE`.
+* Update dependency bounds: clash-prelude-1.10, GHC 9.10
+  * `clash-prelude >= 1.2.5 && < 1.11`
+  * `base >= 4.12 && < 4.21`
+* Test GHC 9.8 and 9.10 in CI
+
 ## 0.3.1.4 -- 2024-01-15
 * Update dependency bounds: clash-prelude-1.8
 

diff --git a/ice40-prim.cabal b/ice40-prim.cabal
@@ -32,9 +32,9 @@ library
                          Ice40.Spi,
                          Ice40.Spram
         hs-source-dirs: src
-        build-depends: base          >= 4.12  && < 4.20,
+        build-depends: base          >= 4.12  && < 4.21,
                        interpolate   >= 0.2   && < 0.3,
-                       clash-prelude >= 1.2.5 && < 1.9,
+                       clash-prelude >= 1.2.5 && < 1.11,
                        ghc-typelits-natnormalise,
                        ghc-typelits-extra,
                        ghc-typelits-knownnat

diff --git a/src/Ice40/GB.hs b/src/Ice40/GB.hs
@@ -1,3 +1,4 @@
+{-# LANGUAGE CPP #-}
 {-|
 Module      : Ice40.GB
 Description : Ice40 Global Buffer IP primtive
@@ -36,6 +37,10 @@ import Data.String.Interpolate.Util (unindent)
   |]) #-}
 
 -- | Global buffer primitive
+#if __GLASGOW_HASKELL__ >= 904
+{-# OPAQUE gbPrim #-}
+#else
 {-# NOINLINE gbPrim #-}
+#endif
 gbPrim :: Clock dom -> Clock dom
 gbPrim !clk = clk
diff --git a/src/Ice40/I2c.hs b/src/Ice40/I2c.hs
@@ -1,3 +1,4 @@
+{-# LANGUAGE CPP #-}
 {-|
 Module      : Ice40.I2c
 Description : Ice40 I2C hard IP primitive
@@ -135,7 +136,11 @@ import Data.String.Interpolate.Util (unindent)
   ]
   |]) #-}
 
+#if __GLASGOW_HASKELL__ >= 904
+{-# OPAQUE i2cPrim #-}
+#else
 {-# NOINLINE i2cPrim #-}
+#endif
 i2cPrim
   :: String          -- ARG[0]  initAddr
   -> String          -- ARG[1]  busAddr

diff --git a/src/Ice40/IO.hs b/src/Ice40/IO.hs
@@ -1,3 +1,4 @@
+{-# LANGUAGE CPP #-}
 {-|
 Module      : Ice40.IO
 Description : Ice40 IO hard IP primitives
@@ -67,7 +68,11 @@ import Data.String.Interpolate.Util (unindent)
   |]) #-}
 
 -- | IO primitive, see io for wrapper
+#if __GLASGOW_HASKELL__ >= 904
+{-# OPAQUE ioPrim #-}
+#else
 {-# NOINLINE ioPrim #-}
+#endif
 ioPrim
   :: BitVector 6         -- ^ pinType
   -> Bit                 -- ^ pullup

diff --git a/src/Ice40/Led.hs b/src/Ice40/Led.hs
@@ -1,3 +1,4 @@
+{-# LANGUAGE CPP #-}
 {-|
 Module      : Ice40.Led
 Description : LED Ice40 hard IP primitive
@@ -79,7 +80,11 @@ import Data.String.Interpolate.Util (unindent)
   ]
   |]) #-}
 
+#if __GLASGOW_HASKELL__ >= 904
+{-# OPAQUE ledPrim #-}
+#else
 {-# NOINLINE ledPrim #-}
+#endif
 ledPrim
   :: Signal dom Bit       -- ARG[0]  leddcs - CS to write LEDD IP registers
   -> Clock dom            -- ARG[1]  leddclk - Clock to write LEDD IP registers

diff --git a/src/Ice40/Mac/Prim.hs b/src/Ice40/Mac/Prim.hs
@@ -1,3 +1,4 @@
+{-# LANGUAGE CPP #-}
 {-|
 Module      : Ice40.Mac.Prim
 Description : Ice40 Multiply-Accumulate (DSP) hard IP primitive
@@ -134,7 +135,11 @@ import Data.String.Interpolate.Util (unindent)
   |]) #-}
 
 -- | Multiply-Accumulate primitive
+#if __GLASGOW_HASKELL__ >= 904
+{-# OPAQUE macPrim #-}
+#else
 {-# NOINLINE macPrim #-}
+#endif
 macPrim
   :: Bit                         -- ^ negTrigger
   -> Bit                         -- ^ aReg

diff --git a/src/Ice40/Osc.hs b/src/Ice40/Osc.hs
@@ -1,3 +1,4 @@
+{-# LANGUAGE CPP #-}
 {-|
 Module      : Ice40.Osc
 Description : Ice40 oscillator hard IP primitives
@@ -49,7 +50,11 @@ import Ice40.Clock
   |]) #-}
 
 -- | Low frequency oscillator 10 kHz
+#if __GLASGOW_HASKELL__ >= 904
+{-# OPAQUE lf10kHz #-}
+#else
 {-# NOINLINE lf10kHz #-}
+#endif
 lf10kHz
   :: Signal dom Bool -- ^ CLKLFPU - Power up the LFOSC circuit. After power up, oscillator output will be stable after 100us. Active High.
   -> Signal dom Bool -- ^ CLKLFEN - Enable the clock output. Enable should be low for the 100us power up period. Active High.
@@ -86,7 +91,11 @@ lf10kHz !_ !_ = Clock SSymbol Nothing
   ]
   |]) #-}
 
+#if __GLASGOW_HASKELL__ >= 904
+{-# OPAQUE hfPrim #-}
+#else
 {-# NOINLINE hfPrim #-}
+#endif
 hfPrim
   :: KnownDomain dom            -- ARG[0]
   => KnownDomain dom'           -- ARG[1]

diff --git a/src/Ice40/Pll/Core.hs b/src/Ice40/Pll/Core.hs
@@ -1,3 +1,4 @@
+{-# LANGUAGE CPP #-}
 {-|
 Module      : Ice40.Pll.Core
 Description : Ice40 PLL hard IP primitive
@@ -76,7 +77,11 @@ import Data.String.Interpolate.Util (unindent)
   |]) #-}
 
 -- | PLL Core primitive
+#if __GLASGOW_HASKELL__ >= 904
+{-# OPAQUE pllCorePrim #-}
+#else
 {-# NOINLINE pllCorePrim #-}
+#endif
 pllCorePrim 
   :: KnownDomain dom'            -- ARG[0]
   => BitVector 7                 -- ^ divf

diff --git a/src/Ice40/Pll/Pad.hs b/src/Ice40/Pll/Pad.hs
@@ -1,3 +1,4 @@
+{-# LANGUAGE CPP #-}
 {-|
 Module      : Ice40.Pll.Pad
 Description : Ice40 PLL Pad hard IP primitive
@@ -77,7 +78,11 @@ import Data.String.Interpolate.Util (unindent)
   |]) #-}
 
 -- | PLL Pad primitive
+#if __GLASGOW_HASKELL__ >= 904
+{-# OPAQUE pllPadPrim #-}
+#else
 {-# NOINLINE pllPadPrim #-}
+#endif
 pllPadPrim 
   :: KnownDomain dom'         -- ARG[0]
   => BitVector 7              -- ^ divf

diff --git a/src/Ice40/Rgb.hs b/src/Ice40/Rgb.hs
@@ -1,3 +1,4 @@
+{-# LANGUAGE CPP #-}
 {-|
 Module      : Ice40.Rgb
 Description : Ice40 RGB hard IP primitive
@@ -88,7 +89,11 @@ import Data.String.Interpolate.Util (unindent)
 --   +-----------------------+-------------------+-------------------+
 --   | "0b111111"            | 24mA              | 12mA              |
 --   +-----------------------+-------------------+-------------------+
+#if __GLASGOW_HASKELL__ >= 904
+{-# OPAQUE rgbPrim #-}
+#else
 {-# NOINLINE rgbPrim #-}
+#endif
 rgbPrim
   :: String           -- ^ currentMode - Parameter values: "0b0" = Full Current Mode (Default), "0b1" = Half Current Mode.
   -> String           -- ^ rgb0Current

diff --git a/src/Ice40/Spi.hs b/src/Ice40/Spi.hs
@@ -1,3 +1,4 @@
+{-# LANGUAGE CPP #-}
 {-|
 Module      : Ice40.Spi
 Description : Ice40 SPI hard IP primitive
@@ -227,7 +228,11 @@ bitAt n = fmap (! n)
   ]
   |]) #-}
 
+#if __GLASGOW_HASKELL__ >= 904
+{-# OPAQUE spiPrim #-}
+#else
 {-# NOINLINE spiPrim #-}
+#endif
 spiPrim
   :: String          -- ARG[0]  busAddr
   -> Clock dom       -- ARG[1]  sbclki

diff --git a/src/Ice40/Spram.hs b/src/Ice40/Spram.hs
@@ -1,3 +1,4 @@
+{-# LANGUAGE CPP #-}
 {-|
 Module      : Ice40.Spram
 Description : Ice40 single-port RAM hard IP primitive
@@ -54,7 +55,11 @@ import Data.String.Interpolate.Util (unindent)
 data Nyb = Nyb3 | Nyb2 | Nyb1 | Nyb0
 
 -- | Single port RAM primitive
+#if __GLASGOW_HASKELL__ >= 904
+{-# OPAQUE spramPrim #-}
+#else
 {-# NOINLINE spramPrim #-}
+#endif
 spramPrim
   :: KnownDomain dom            -- ARG[0] 
   => Clock dom                  -- ^ clock