Test of many possible configuration settings with the goal of improving VexRiscV RTL performance at minimal cost for FPGA area.
Performance is compared using Coremark.
The RTLs were built based on the internal tinyVision.ai SoC and may not directly match results using different setups. The bare numbers measure the whole of the SoC, this includes some peripherals (usually, USB, UART and I2C, plus what is needed to support the core), so is not suitable to compare directly to area usage of a core only, but only to the same configuration.
Core frequency is 65MHz unless mentionned to be something else.
Change the cache to have 2 ways and to be bigger as needed by 2 ways.
Gains observed, more area and memory usage observed.
new RegFilePlugin(
regFileReadyKind = plugin.ASYNC,
zeroBoot = true
),
config = InstructionCacheConfig(
cacheSize = 4096,
bytePerLine = 32,
wayCount = 2,
addressWidth = 32,
cpuDataWidth = 32,
memDataWidth = 32,
catchIllegalAccess = true,
catchAccessFault = true,
asyncTagMemory = false,
twoCycleRam = true,
twoCycleCache = true
),
'Enable' early branching in BranchPlugin
No gains observed, more area usage observed.
new BranchPlugin(
earlyBranch = true,
Effectively enable early branching by switching on DYNAMIC_TARGET in the instruction cache configuration.
Gains observed, more area usage observed.
new BranchPlugin(
earlyBranch = true,
new IBusCachedPlugin(
...
prediction = DYNAMIC_TARGET,
Replace LightShifterPlugin with the faster FullBarrelShifterPlugin
Gains observed, more area usage observed.
- new LightShifterPlugin,
+ new FullBarrelShifterPlugin,
Disable relaxed Program Counter Calculations
Gains observed, less area usage observed.
new IBusCachedPlugin(
...
relaxedPcCalculation = false,
separatedAddSub to true in SrcPlugin
No gains observed, bigger area usage observed.
new SrcPlugin(
separatedAddSub = true,
Change MulDivIterativePlugin instances with MulPlugin and DivPlugin.
Internally MulPlugin is different from MulDivIterativePlugin, but DivPlugin the same thing.
Significant gains observed, bigger area usage observed, usage of lattice DSP units observed.
4 Units of DSP 18x18 multiplication as used to fulfill 'Do partial multiplication, four times 16 bits * 16 bits' in the RTL code.
- (genMul || genDiv) generate new MulDivIterativePlugin(
- genMul = genMul,
- genDiv = genDiv,
- mulUnrollFactor = 1,
- divUnrollFactor = 1
- ),
+ new MulPlugin,
+ new DivPlugin,
mulUnrollFactor to 4
Things that were attempted but unable to complete:
- Changing XIP Flash clock speed
- Adding DCache
- Enabling LRAM latency register to increase clock speed (they were already enabled)
- Disabling 'logger' for more clock speed, possibly a misunderstanding of timing report and code
The benchmarks were ran with CONFIG_SPEED_OPTIMIZATIONS=y, and additionally CONFIG_CODE_DATA_RELOCATE=y and a CMake bit relocation the benchmark code to RAM for 'RAM' results.
| Name | Modifications | XIP score | RAM score | RAM coremark/Mhz |
|---|---|---|---|---|
| rp2040 125MHz (for reference) | - | 230 | 230 | 1.84 |
| Litex 80 MHz (for reference) | - | 68 | 73 | 0.912 |
| SpineX Reference | - | 50 | 55 | 0.84 |
| 2 ways icache | bigcache | 52 | 55 | 0.84 |
| earlybranch | (earlybranch) | 50 | 55 | 0.84 |
| earlybranch_DYNAMIC_TARGET | earlybranch | 52 | 57 | 0.876 |
| mulratio | mulratio | 61 | 68 | 1.04 |
| - | fullbarrel | 64 | 73 | 1.12 |
| earlybranch_DYNAMIC_TARGET_fullbarrelshifter | earlybranch, fullbarrel | - | - | - |
| fullbarrellshifter_norelax | fullbarrel, norelax | 68 | 78 | 1.2 |
| fbnorelax_sepsubadd | fullbarrel, norelax, sepsubadd | - | - | - |
| fullbarrellshifter_norelax_bigcache | fullbarrel, norelax, bigcache | 78 | 84 | 1.29 |
| fbnorelax_branchpred_bigcache_72Mhz (72MHz) | fullbarrel, norelax, bigcache, earlybranch | 84 | 91 | 1.4 |
| fullbarrellshifter_norelax_muldiv | fullbarrel, norelax, muldiv | 100 | 117 | 1.8 |
| - (72MHz) | fullbarrel, norelax, bigcache, muldiv | - | 142 | 1.97 |
Device utilization summary:
VHI 1/1 100% used
EBR 4/64 6% used
LRAM 3/5 60% used
SEIO18 1/32 3% used
1/32 3% bonded
SEIO33 16/51 31% used
16/19 84% bonded
PLL 1/1 100% used
CONFIG_WDT 1/1 100% used
APIO 10/16 63% used
USB23 1/1 100% used
SLICE 10367/13824 75% used
LUT 9363/27648 34% used
REG 6295/27648 23% used
Device utilization summary:
VHI 1/1 100% used
EBR 4/64 6% used
LRAM 3/5 60% used
SEIO18 1/32 3% used
1/32 3% bonded
SEIO33 16/51 31% used
16/19 84% bonded
PLL 1/1 100% used
CONFIG_WDT 1/1 100% used
APIO 10/16 63% used
USB23 1/1 100% used
SLICE 10367/13824 75% used
LUT 9493/27648 34% used
REG 6325/27648 23% used
Device utilization summary:
VHI 1/1 100% used
EBR 4/64 6% used
LRAM 3/5 60% used
SEIO18 1/32 3% used
1/32 3% bonded
SEIO33 16/51 31% used
16/19 84% bonded
PLL 1/1 100% used
CONFIG_WDT 1/1 100% used
APIO 10/16 63% used
USB23 1/1 100% used
SLICE 10367/13824 75% used
LUT 9472/27648 34% used
REG 6212/27648 22% used
Device utilization summary:
VHI 1/1 100% used
EBR 4/64 6% used
MULT9 8/128 6% used
MULT18 4/64 6% used
REG18 8/128 6% used
PREADD9 8/128 6% used
LRAM 3/5 60% used
SEIO18 1/32 3% used
1/32 3% bonded
SEIO33 16/51 31% used
16/19 84% bonded
PLL 1/1 100% used
CONFIG_WDT 1/1 100% used
APIO 10/16 63% used
USB23 1/1 100% used
SLICE 10367/13824 75% used
LUT 9711/27648 35% used
REG 6350/27648 23% used
Device utilization summary:
VHI 1/1 100% used
EBR 8/64 13% used
LRAM 3/5 60% used
SEIO18 1/32 3% used
1/32 3% bonded
SEIO33 16/51 31% used
16/19 84% bonded
PLL 1/1 100% used
CONFIG_WDT 1/1 100% used
APIO 10/16 63% used
USB23 1/1 100% used
SLICE 10367/13824 75% used
LUT 9375/27648 34% used
REG 6413/27648 23% used
Device utilization summary:
VHI 1/1 100% used
EBR 4/64 6% used
LRAM 3/5 60% used
SEIO18 1/32 3% used
1/32 3% bonded
SEIO33 16/51 31% used
16/19 84% bonded
PLL 1/1 100% used
CONFIG_WDT 1/1 100% used
APIO 10/16 63% used
USB23 1/1 100% used
SLICE 10367/13824 75% used
LUT 9598/27648 35% used
REG 6439/27648 23% used
Different revision.
Device utilization summary:
VHI 1/1 100% used
EBR 35/64 55% used
LRAM 5/5 100% used
SEIO18 1/32 3% used
1/32 3% bonded
SEIO33 16/51 31% used
16/19 84% bonded
PLL 1/1 100% used
CONFIG_WDT 1/1 100% used
APIO 10/16 63% used
USB23 1/1 100% used
SLICE 10367/13824 75% used
LUT 11895/27648 43% used
REG 8908/27648 32% used