MoE: Add fused additive EXL3 kernels

[malaiwah]

Summary

Add a graph-capturable additive EXL3 MoE path for compressed residual ("cartridge") stages.

• extend exl3_gemm_inner with FP32 accumulation and output scaling
• add exl3_moe_additive for callers that already have route metadata
• add exl3_moe_additive_fused for stable route packing plus base/residual execution in one extension call
• export EXL3_MOE_ADDITIVE_ABI_VERSION = 1 for exact consumer compatibility checks
• tile oversized expert route spans within the fixed scratch workspace
• support stage-major trellis pointer, scale, and bitrate tables with zero-scale sparse entries
• validate CUDA device, contiguity, dtype, shape, workspace, and routing contracts before device-side mutation
• preserve the existing exl3_moe ABI and legacy overflow fallback behavior

API contract

Consumers must require an exact supported EXL3_MOE_ADDITIVE_ABI_VERSION; symbol presence or callable arity is not a compatibility contract. The version is bumped for incompatible signature, pointer-layout, routing-workspace, residual-encoding, or overflow-semantics changes.

Additive residual trellises use the MCG codebook and reuse each base projection's suh/svh rotations. Their K metadata must be validated by the caller before graph capture. A zero scale skips that projection's GEMM.

The int64 pointer tables do not retain their pointees. Callers must keep all referenced trellis and rotation allocations alive, unmoved, and on the same device through asynchronous completion and for the lifetime of a captured graph.

For additive calls, num_active is only a launch-size hint and counts every nonempty expert. Oversized experts are processed in workspace-sized tiles, so rows * topk scratch is not required.

Relationship to #246

The fused route histogram, scan, and stable-packing pipeline is adapted from @brandonmmusic-max's draft #246 (commit 704aefd) and rebased onto the current ticket-scheduled MoE kernel. This PR does not include #246's SM120 retile; it adds additive residual stages. Brandon is credited in the squashed commit.

Companion work

• runtime consumer: local-inference-lab/vllm#299
• cartridge producer: malaiwah/progressive-tensors#41

This PR is intentionally limited to the extension compute/API layer; it does not define the on-disk cartridge manifest. Consumers remain responsible for validating artifact version, extension ABI, codebook, K values, coverage, and pointer lifetime before invoking the extension.

Validation

Direct extension validation on NVIDIA L4 (SM89), CUDA 12.6, and PyTorch 2.6:

• full setup.py build_ext --inplace completed successfully
• python -m pytest -q tests/test_exl3_moe_additive.py: 14 passed
• covers int32/int64 route IDs; FP16/BF16/FP32 route weights; stable packing; exactly capacity + 1 and multi-tile overflow; the downstream topk=2, capacity=rows case; zero-scale/null sparse stages; and preserved legacy overflow behavior

The ABI-version follow-up is a header/binding/test-only change. git diff --check and Python syntax validation pass; the CUDA behavior is unchanged from the L4-tested commit.

Earlier downstream prototype validation on RTX 5090 (SM120), CUDA 12.8, and PyTorch 2.8 reported successful CUDA-graph capture and base -> cartridge -> base transitions. Restored base logprobs matched exactly (max_abs=0.0); packed-vs-dense cartridge output had mean KL 1.30506e-4, max absolute logit delta 0.11122, mean absolute logit delta 0.00910, and identical argmax on sampled prompts.

AI assistance was used. I reviewed the source changes and validation results.

[brandonmmusic-max]

Thank you for the attribution