target/mips: add partial Cavium Octeon (cnMIPS) instruction support#2318
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retrocpugeek wants to merge 4 commits into
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target/mips: add partial Cavium Octeon (cnMIPS) instruction support#2318retrocpugeek wants to merge 4 commits into
retrocpugeek wants to merge 4 commits into
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* - Fix JAVA binding compilation: Apparently, the pointer there is a leftover from the previous implementation. Fails to build on OSX. * - Fix m68k regression test, probably needs updating as a result of unicorn-engine#2161. * - Fix the Java regression testing, probably as a result of fixing unicorn-engine#2161. --------- Co-authored-by: mac <mac@MacBook-Pro-mac-2.local>
Octeon userspace (e.g. OpenWrt busybox built for mips64_octeonplus)
frequently emits cnMIPS-specific ops that trapped as Reserved
Instruction on every existing MIPS64 CPU model. This patch adds the
subset used by typical Octeon-Plus integer userspace:
BBIT0 / BBIT032 / BBIT1 / BBIT132 (primary opcodes 0x32 / 0x36 /
0x3A / 0x3E, reusing non-R6
LWC2/LDC2/SWC2/SDC2 slots)
CINS / CINS32 (SPECIAL2 func 0x32 / 0x33)
EXTS / EXTS32 (SPECIAL2 func 0x3A / 0x3B)
DMUL (SPECIAL2 func 0x03)
SEQ / SNE (SPECIAL2 func 0x2A / 0x2B)
SEQI / SNEI (SPECIAL2 func 0x2E / 0x2F)
All codegen uses existing TCG primitives (tcg_gen_setcond,
tcg_gen_mul_tl, tcg_gen_deposit_z_tl, tcg_gen_sextract_tl,
tcg_gen_extract_tl) and reuses the standard MIPS branch bookkeeping for
BBIT delay slots. Instruction behaviour matches the CN50XX HRM
(§ "Cavium Networks-Specific Instruction Descriptions", pages 827-937).
A new coarse INSN_OCTEON flag gates the dispatch cases, and a new
"Octeon-Plus" CPU model (PRId=0x000d0600 per HRM: CompanyID=0x0d,
ProcessorID=0x06 for CN50XX) is exposed as UC_CPU_MIPS64_OCTEON_PLUS.
Not implemented in this patch (still trap as RI): BADDU, POP/DPOP,
SAA/SAAD, SYNCS/SYNCW/SYNCIOBDMA, the CVM_MT_*/CVM_MF_* COP2 crypto
ops, Octeon MMI, and all Octeon II (CN6XXX) additions.
Tests: bindings/python/tests/test_mips_octeon.py covers all nine new
mnemonics including taken/not-taken paths for each BBIT variant.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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Summary
Adds partial Cavium Octeon (cnMIPS) instruction support so that Octeon userspace (e.g. OpenWrt busybox for
mips64_octeonplus) no longer traps on common integer ops.Implemented:
bbit0,bbit032,bbit1,bbit132,cins,cins32,exts,exts32,dmul,seq,sne,seqi,snei.Not implemented (still trap as RI):
baddu,pop/dpop,saa/saad,syncs/syncw/synciobdma, theCVM_MT_*/CVM_MF_*COP2 crypto ops, Octeon MMI, any Octeon II (CN6XXX) additions.Behaviour follows CN50XX HRM §"Cavium Networks-Specific Instruction Descriptions" (pages 827–937).
A new
INSN_OCTEONISA flag gates the dispatch cases; a newUC_CPU_MIPS64_OCTEON_PLUSCPU model exposes the extensions (PRId0x000d0600, CompanyID0x0d/ ProcessorID0x06per HRM).Test plan
bindings/python/tests/test_mips_octeon.py— 22 unit tests (all nine mnemonics, plus taken/not-taken paths for each BBIT variant)mips64_octeonplus_64_musl(function usingextsin a delay slot)INSN_OCTEONis set)