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1. My-Portfolio My-Portfolio Public

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2. AI-ML-Based-Digital-Loop-Filter-for-ADPLL AI-ML-Based-Digital-Loop-Filter-for-ADPLL Public

   An All-Digital PLL (UMC 180nm) with a 25th-order FIR digital loop filter whose coefficients are trained by an ANN — achieving 2.26 GHz output, 8 ns lock time, and 5.3 mW power.

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3. uart-rtl2gds-scl180 uart-rtl2gds-scl180 Public

   Full RTL-to-GDS ASIC flow for a UART IP on SCL 180nm (Genus + Innovus). 293 cells, 42,910 µm², 32.2 µW, 0 DRC violations, 8.275 ns signoff slack - verified via RTL sim, GLS, and formal LEC.

   Verilog 1

4. Edge_AI_Based_Arrhythmia_Detection_on_FPGA Edge_AI_Based_Arrhythmia_Detection_on_FPGA Public

   1D-CNN ECG arrhythmia classifier (5-class, MIT-BIH) trained in PyTorch, quantized to INT8, and deployed on Xilinx Artix-7 (xc7a35t) FPGA. ~82% accuracy,~60 KB model, runs upto 72 MHz with 0 failing…

   Jupyter Notebook 1