Fix simx flush arbiter - #391
Conversation
TFifo::empty() reports only entries that have emerged from the pipe's latency window (SimChannel::queue_empty ignores pending_count_), so processFlush()'s drain guard could not see a replayed store pushed into pipe_req_ earlier in the same tick. The walk then swept the store's set while its line was still clean and finished before the write applied, losing the store on an end-of-kernel flush. Observed with vm_stress on simx/XLEN=32 once the VM MMU model added translation latency, but the window is generic to any replay that lands as the flush starts; size() counts in-flight entries and closes it. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
TxArbiter and TxRxArbiter sized their per-output request group with log2ceil(num_inputs / num_outputs); when the input count is not a multiple of the output count that rounds down and the trailing inputs are never polled (VX_stream_arb uses CDIV). Callers had to pad input counts up to a power-of-two multiple to work around it. Also adds the CHANGELOG entry for the cache flush-walk fix. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
|
Reviewed and accepted — thank you, this is a real bug and the diagnosis was correct. VerificationReproduced on master before the fix. The shape that breaks is any request count that is not a 3 cores over 2 shared icaches → Why CI missed itEvery catalog case that shares an icache used a power-of-two core:cache ratio, so - id: demo-shared-icache-odd
via: blackbox
drivers: [simx]
app: demo
configs: -DVX_CFG_SOCKET_SIZE=3 -DVX_CFG_NUM_ICACHES=2
shape: { cores: 3 }Validated both ways: it hangs under floor grouping and passes under ceiling grouping. What landed
The other half of this PR — the cache-flush walk gating on |
some bug fixes that arose when testing VM work