Cmake rework

DirectProgramming/DPC++FPGA/Tutorials/Features/loop_unroll/CMakeLists.txt

@@ -1,20 +1,181 @@
+# Direct CMake to use icpx rather than the default C++ compiler/linker on Linux
+# and icx-cl on Windows
 if(UNIX)
-    # Direct CMake to use icpx rather than the default C++ compiler/linker
     set(CMAKE_CXX_COMPILER icpx)
 else() # Windows
-    # Force CMake to use icx-cl rather than the default C++ compiler/linker 
-    # (needed on Windows only)
     include (CMakeForceCompiler)
     CMAKE_FORCE_CXX_COMPILER (icx-cl IntelDPCPP)
     include (Platform/Windows-Clang)
 endif()
 
-cmake_minimum_required (VERSION 3.4)
+cmake_minimum_required (VERSION 3.7.2)
 
 project(LoopUnroll CXX)
 
 set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR})
 set(CMAKE_LIBRARY_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR})
 set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR})
 
-add_subdirectory (src)
+###############################################################################
+### Customize these build variables
+###############################################################################
+set(SOURCE_FILE src/loop_unroll.cpp)
+set(TARGET_NAME loop_unroll)
+
+# Use cmake -DFPGA_DEVICE=<board-support-package>:<board-variant> to choose a
+# different device. Here are a few device examples (this list is not
+# exhaustive):
+#   intel_s10sx_pac:pac_s10
+#   intel_s10sx_pac:pac_s10_usm
+#   intel_a10gx_pac:pac_a10
+# Note that depending on your installation, you may need to specify the full 
+# path to the board support package (BSP), this usually is in your install 
+# folder.
+#
+# You can also specify a device family (E.g. "Arria10" or "Stratix10") or a
+# specific part number (E.g. "10AS066N3F40E2SG") to generate a standalone IP.
+if(NOT DEFINED FPGA_DEVICE)
+    set(FPGA_DEVICE "intel_s10sx_pac:pac_s10_usm")
+endif()
+
+# Use cmake -DUSER_FPGA_FLAGS=<flags> to set extra flags for FPGA backend
+# compilation. 
+set(USER_FPGA_FLAGS "${USER_FPGA_FLAGS}")
+
+# Use cmake -DUSER_FLAGS=<flags> to set extra flags for general compilation.
+set(USER_FLAGS "${USER_FLAGS}")
+
+# Use cmake -DUSER_INCLUDE_PATHS=<paths> to set extra paths for general
+# compilation.
+set(USER_INCLUDE_PATHS "${USER_INCLUDE_PATHS}")
+
+# Specify the location of the FPGA include directory
+set(FPGA_INCLUDE_PATHS ../../../include)
+
+###############################################################################
+### no changes after here
+###############################################################################
+
+# Make cmake export the compile_commands.json file that contains the 
+# compile commands of each target
+set(CMAKE_EXPORT_COMPILE_COMMANDS ON)
+
+# Print the device being used for the compiles
+message(STATUS "Configuring the design to run on FPGA board ${FPGA_DEVICE}")
+
+# Set the names of the makefile targets to be generated by cmake
+set(EMULATOR_TARGET fpga_emu)
+set(SIMULATOR_TARGET fpga_sim)
+set(REPORT_TARGET report)
+set(FPGA_TARGET fpga)
+set(IP_EXPORT_TARGET fpga_ip_export)
+
+# Set the names of the generated files per makefile target
+set(EMULATOR_OUTPUT_NAME ${TARGET_NAME}.${EMULATOR_TARGET})
+set(SIMULATOR_OUTPUT_NAME ${TARGET_NAME}.${SIMULATOR_TARGET})
+set(REPORT_OUTPUT_NAME ${TARGET_NAME}.${REPORT_TARGET})
+set(FPGA_OUTPUT_NAME ${TARGET_NAME}.${FPGA_TARGET})
+
+# Get the user include path
+set(INCLUDEPATHS_LIST ${USER_INCLUDE_PATHS})
+# Add the FPGA include directory location
+list(APPEND INCLUDEPATHS_LIST ${FPGA_INCLUDE_PATHS})
+# Sanitize the include path
+separate_arguments(INCLUDEPATHS_LIST)
+include_directories(${INCLUDEPATHS_LIST})
+
+# This is a Windows-specific flag that enables exception handling in host code
+if(WIN32)
+    # add qactypes to link command on Windows only
+    set(QACTYPES "/Qactypes")
+    set(WIN_FLAG "/EHsc")
+else()
+    # add qactypes for Linux
+    set(QACTYPES "-qactypes")
+endif()
+
+set(COMMON_COMPILE_FLAGS -fsycl -fintelfpga -Wall ${WIN_FLAG} ${QACTYPES})
+set(COMMON_LINK_FLAGS -fsycl -fintelfpga ${QACTYPES})
+
+# A SYCL ahead-of-time (AoT) compile processes the device code in two stages.
+# 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V).
+# 2. The "link" stage invokes the compiler's FPGA backend before linking.
+#    For this reason, FPGA backend flags must be passed as link flags in CMake.
+set(EMULATOR_COMPILE_FLAGS -DFPGA_EMULATOR)
+set(EMULATOR_LINK_FLAGS )
+set(REPORT_COMPILE_FLAGS -DFPGA_HARDWARE)
+set(REPORT_LINK_FLAGS -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS} -fsycl-link=early)
+set(SIMULATOR_COMPILE_FLAGS -Xssimulation -DFPGA_SIMULATOR)
+set(SIMULATOR_LINK_FLAGS -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS})
+set(HARDWARE_COMPILE_FLAGS -DFPGA_HARDWARE)
+set(HARDWARE_LINK_FLAGS -Xshardware -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS} -reuse-exe=${CMAKE_BINARY_DIR}/${FPGA_OUTPUT_NAME})
+# use cmake -D USER_HARDWARE_FLAGS=<flags> to set extra flags for FPGA simulator compilation and backend compilation
+
+###############################################################################
+### FPGA Emulator
+###############################################################################
+add_executable(${EMULATOR_TARGET} ${SOURCE_FILE})
+target_compile_options(${EMULATOR_TARGET} PRIVATE ${COMMON_COMPILE_FLAGS})
+target_compile_options(${EMULATOR_TARGET} PRIVATE ${EMULATOR_COMPILE_FLAGS})
+target_link_libraries(${EMULATOR_TARGET} ${COMMON_LINK_FLAGS})
+target_link_libraries(${EMULATOR_TARGET} ${EMULATOR_LINK_FLAGS})
+set_target_properties(${EMULATOR_TARGET} PROPERTIES OUTPUT_NAME ${EMULATOR_OUTPUT_NAME})
+
+# Make cmake print the locations of the command before building
+add_custom_target( displayEmulationCommands ALL
+    ${CMAKE_COMMAND} -E cmake_echo_color --cyan ""
+    COMMENT "Find the compile command in ${CMAKE_CURRENT_BINARY_DIR}/compile_commands.json (the one using FPGA_EMULATOR) and the link command in ${CMAKE_CURRENT_BINARY_DIR}/CMakeFiles/${EMULATOR_TARGET}.dir/link.txt")
+add_dependencies(${EMULATOR_TARGET} displayEmulationCommands)
+
+###############################################################################
+### FPGA Simulator
+###############################################################################
+add_executable(${SIMULATOR_TARGET} ${SOURCE_FILE})
+target_compile_options(${SIMULATOR_TARGET} PRIVATE ${COMMON_COMPILE_FLAGS})
+target_compile_options(${SIMULATOR_TARGET} PRIVATE ${SIMULATOR_COMPILE_FLAGS})
+target_link_libraries(${SIMULATOR_TARGET} ${COMMON_LINK_FLAGS})
+target_link_libraries(${SIMULATOR_TARGET} ${SIMULATOR_LINK_FLAGS})
+set_target_properties(${SIMULATOR_TARGET} PROPERTIES OUTPUT_NAME ${SIMULATOR_OUTPUT_NAME})
+
+# Make cmake print the locations of the command before building
+add_custom_target( displaySimulationCommands ALL
+    ${CMAKE_COMMAND} -E cmake_echo_color --cyan ""
+    COMMENT "Find the compile command in ${CMAKE_CURRENT_BINARY_DIR}/compile_commands.json (the one using FPGA_SIMULATOR) and the link command in ${CMAKE_CURRENT_BINARY_DIR}/CMakeFiles/${SIMULATOR_TARGET}.dir/link.txt")
+add_dependencies(${SIMULATOR_TARGET} displaySimulationCommands)
+
+###############################################################################
+### Generate Report
+###############################################################################
+add_executable(${REPORT_TARGET} ${SOURCE_FILE})
+target_compile_options(${REPORT_TARGET} PRIVATE ${COMMON_COMPILE_FLAGS})
+target_compile_options(${REPORT_TARGET} PRIVATE ${REPORT_COMPILE_FLAGS})
+
+# The report target does not need the QACTYPES flag at link stage
+set(MODIFIED_COMMON_LINK_FLAGS_REPORT ${COMMON_LINK_FLAGS})
+list(REMOVE_ITEM MODIFIED_COMMON_LINK_FLAGS_REPORT ${QACTYPES})
+
+target_link_libraries(${REPORT_TARGET} ${MODIFIED_COMMON_LINK_FLAGS_REPORT})
+target_link_libraries(${REPORT_TARGET} ${REPORT_LINK_FLAGS})
+set_target_properties(${REPORT_TARGET} PROPERTIES OUTPUT_NAME ${REPORT_OUTPUT_NAME})
+
+# Make cmake print the locations of the command before building
+add_custom_target( displayReportCommands ALL
+    ${CMAKE_COMMAND} -E cmake_echo_color --cyan ""
+    COMMENT "Find the compile command in ${CMAKE_CURRENT_BINARY_DIR}/compile_commands.json (the one using FPGA_HARDWARE with fsycl-link=early) and the link command in ${CMAKE_CURRENT_BINARY_DIR}/CMakeFiles/${REPORT_TARGET}.dir/link.txt")
+add_dependencies(${REPORT_TARGET} displayReportCommands)
+
+###############################################################################
+### FPGA Hardware
+###############################################################################
+add_executable(${FPGA_TARGET} EXCLUDE_FROM_ALL ${SOURCE_FILE})
+target_compile_options(${FPGA_TARGET} PRIVATE ${COMMON_COMPILE_FLAGS})
+target_compile_options(${FPGA_TARGET} PRIVATE ${HARDWARE_COMPILE_FLAGS})
+target_link_libraries(${FPGA_TARGET} ${COMMON_LINK_FLAGS})
+target_link_libraries(${FPGA_TARGET} ${HARDWARE_LINK_FLAGS})
+set_target_properties(${FPGA_TARGET} PROPERTIES OUTPUT_NAME ${FPGA_OUTPUT_NAME})
+
+# Make cmake print the locations of the command before building
+add_custom_target( displayFPGACommands ALL
+    ${CMAKE_COMMAND} -E cmake_echo_color --cyan ""
+    COMMENT "Find the compile command in ${CMAKE_CURRENT_BINARY_DIR}/compile_commands.json (the one using FPGA_HARDWARE without fsycl-link=early) and the link command in ${CMAKE_CURRENT_BINARY_DIR}/CMakeFiles/${FPGA_TARGET}.dir/link.txt")
+add_dependencies(${FPGA_TARGET} displayFPGACommands)

DirectProgramming/DPC++FPGA/Tutorials/Features/loop_unroll/README.md

@@ -125,95 +125,75 @@ The basic steps to build and run a sample using VS Code include:
 To learn more about the extensions and how to configure the oneAPI environment, see the 
 [Using Visual Studio Code with Intel® oneAPI Toolkits User Guide](https://software.intel.com/content/www/us/en/develop/documentation/using-vs-code-with-intel-oneapi/top.html).
 
-### On a Linux* System
-
-1. Generate the `Makefile` by running `cmake`.
-     ```
-   mkdir build
-   cd build
-   ```
-   To compile for the Intel® PAC with Intel Arria® 10 GX FPGA, run `cmake` using the command:
-    ```
-    cmake ..
-   ```
-   Alternatively, to compile for the Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX), run `cmake` using the command:
-
-   ```
-   cmake .. -DFPGA_DEVICE=intel_s10sx_pac:pac_s10
-   ```
-   You can also compile for a custom FPGA platform. Ensure that the board support package is installed on your system. Then run `cmake` using the command:
-   ```
-   cmake .. -DFPGA_DEVICE=<board-support-package>:<board-variant>
-   ```
-
-2. Compile the design through the generated `Makefile`. The following build targets are provided, matching the recommended development flow:
-
-   * Compile for emulation (fast compile time, targets emulated FPGA device):
-     ```
-     make fpga_emu
-     ```
-   * Compile for simulation (fast compile time, targets simulator FPGA device):
-     ```
-     make fpga_sim
-     ```
-   * Generate the optimization report:
-     ```
-     make report
-     ```
-   * Compile for FPGA hardware (longer compile time, targets FPGA device):
-     ```
-     make fpga
-     ```
-3. (Optional) As the above hardware compile may take several hours to complete, FPGA precompiled binaries (compatible with Linux* Ubuntu* 18.04) can be downloaded <a href="https://iotdk.intel.com/fpga-precompiled-binaries/latest/loop_unroll.fpga.tar.gz" download>here</a>.
+### Configure the build system
+
+Create and go to a build directory
+```
+mkdir build
+cd build
+```
+
+#### On a Linux* System
+
+To configure the build system for the Intel&reg; PAC with Intel Arria&reg; 10 GX FPGA, run `cmake` using the command:
+```
+cmake ..
+```
+Alternatively, to configure the build system for the Intel&reg; FPGA PAC D5005 (with Intel Stratix&reg; 10 SX), run `cmake` using the command:
 
-### On a Windows* System
-
-1. Generate the `Makefile` by running `cmake`.
-     ```
-   mkdir build
-   cd build
-   ```
-   To compile for the Intel&reg; PAC with Intel Arria&reg; 10 GX FPGA, run `cmake` using the command:
-    ```
-    cmake -G "NMake Makefiles" ..
-   ```
-   Alternatively, to compile for the Intel&reg; FPGA PAC D5005 (with Intel Stratix&reg; 10 SX), run `cmake` using the command:
-
-   ```
-   cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=intel_s10sx_pac:pac_s10
-   ```
-   You can also compile for a custom FPGA platform. Ensure that the board support package is installed on your system. Then run `cmake` using the command:
-   ```
-   cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=<board-support-package>:<board-variant>
-   ```
-
-2. Compile the design through the generated `Makefile`. The following build targets are provided, matching the recommended development flow:
-
-   * Compile for emulation (fast compile time, targets emulated FPGA device):
-     ```
-     nmake fpga_emu
-     ```
-   * Compile for simulation (fast compile time, targets simulator FPGA device):
-     ```
-     nmake fpga_sim
-     ```
-   * Generate the optimization report:
-     ```
-     nmake report
-     ```
-   * Compile for FPGA hardware (longer compile time, targets FPGA device):
-     ```
-     nmake fpga
-     ```
+```
+cmake .. -DFPGA_DEVICE=intel_s10sx_pac:pac_s10
+```
+You can also configure the build system for a custom FPGA platform. Ensure that the board support package is installed on your system. Then run `cmake` using the command:
+```
+cmake .. -DFPGA_DEVICE=<board-support-package>:<board-variant>
+```
+
+#### On a Windows* System
+To configure the build system for the Intel&reg; PAC with Intel Arria&reg; 10 GX FPGA, run `cmake` using the command:
+```
+cmake -G "NMake Makefiles" ..
+```
+Alternatively, to configure the build system for the Intel&reg; FPGA PAC D5005 (with Intel Stratix&reg; 10 SX), run `cmake` using the command:
+
+```
+cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=intel_s10sx_pac:pac_s10
+```
+You can also configure the build system for a custom FPGA platform. Ensure that the board support package is installed on your system. Then run `cmake` using the command:
+```
+cmake -G "NMake Makefiles" .. -DFPGA_DEVICE=<board-support-package>:<board-variant>
+```
+
+### Compile the design
+
+
+* Compile for emulation (fast compile time, targets emulated FPGA device):
+  ```
+  cmake --build . --target fpga_emu
+  ```
+* Compile for simulation (fast compile time, targets simulator FPGA device):
+  ```
+  cmake --build . --target fpga_sim
+  ```
+* Generate the optimization report:
+  ```
+  cmake --build . --target report
+  ```
+* Compile for FPGA hardware (longer compile time, targets FPGA device):
+  ```
+  cmake --build . --target fpga
+  ```
+
+3. (Optional) As the above hardware compile may take several hours to complete, FPGA precompiled binaries (compatible with Linux* Ubuntu* 18.04) can be downloaded <a href="https://iotdk.intel.com/fpga-precompiled-binaries/latest/loop_unroll.fpga.tar.gz" download>here</a>.
 
 > **Note**: The Intel&reg; PAC with Intel Arria&reg; 10 GX FPGA and Intel&reg; FPGA PAC D5005 (with Intel Stratix&reg; 10 SX) do not support Windows*. Compiling to FPGA hardware on Windows* requires a third-party or custom Board Support Package (BSP) with Windows* support.
 
 > **Note**: If you encounter any issues with long paths when compiling under Windows*, you may have to create your ‘build’ directory in a shorter path, for example c:\samples\build.  You can then run cmake from that directory, and provide cmake with the full path to your sample directory.
 
 ### Troubleshooting
-If an error occurs, you can get more details by running `make` with
-the `VERBOSE=1` argument:
-``make VERBOSE=1``
+If an error occurs, you can get more details by running `cmake` with
+the `-- VERBOSE=1` argument:
+e.g. ``cmake --build . --target fpga_emu -- VERBOSE=1``
 For more comprehensive troubleshooting, use the Diagnostics Utility for
 Intel&reg; oneAPI Toolkits, which provides system checks to find missing
 dependencies and permissions errors.
@@ -233,20 +213,20 @@ You can also check the achieved system f<sub>MAX</sub> to verify the earlier cal
 ## Running the Sample
 
 1. Run the sample on the FPGA emulator (the kernel executes on the CPU):
-     ```
-     ./loop_unroll.fpga_emu     (Linux)
-     loop_unroll.fpga_emu.exe   (Windows)
-     ```
+  ```
+  ./loop_unroll.fpga_emu     (Linux)
+  loop_unroll.fpga_emu.exe   (Windows)
+  ```
 2. Run the sample on the FPGA simulator device:
-     ```
-     ./loop_unroll.fpga_sim     (Linux)
-     loop_unroll.fpga_sim.exe   (Windows)
-     ```
+  ```
+  ./loop_unroll.fpga_sim     (Linux)
+  loop_unroll.fpga_sim.exe   (Windows)
+  ```
 3. Run the sample on the FPGA device:
-     ```
-     ./loop_unroll.fpga         (Linux)
-     loop_unroll.fpga.exe       (Windows)
-     ```
+  ```
+  ./loop_unroll.fpga         (Linux)
+  loop_unroll.fpga.exe       (Windows)
+  ```
 
 ### Example of Output
 ```