fix: latent cache coherency issues in relocation and cache flush - #392
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Signed-off-by: Jose Martins <josemartins90@gmail.com>
Signed-off-by: Jose Martins <josemartins90@gmail.com>
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cache_flush_range()on armv8 ended with admb, which does not guarantee completion of the cache maintenance operations, while its callers rely on it: the relocation flow before other cores fetch the relocated image, the guest image flush, and the psci off state flush before a core powers down. Replace it with adsb.The riscv
switch_space()never executedfence.i, so instruction fetch is not synchronized with the data-side copy of the relocated image, the same problem #391 fixes for aarch64. Execute it just before thesatpwrite, while still fetching from the original pages. This requires enablingzifenceiin the march string.Both qemu-aarch64-virt and qemu-riscv64-virt builds pass.