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fix: latent cache coherency issues in relocation and cache flush #392

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fix: latent cache coherency issues in relocation and cache flush #392

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07abd8b
fix(armv8): ensure completion of cache flush operations
josecm Aug 7, 2026
1dc70f4
fix(riscv): synchronize instruction fetch when switching address space
josecm Aug 7, 2026
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3 changes: 2 additions & 1 deletion src/arch/armv8/cache.c
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Original file line number Diff line number Diff line change
Expand Up @@ -114,5 +114,6 @@ void cache_flush_range(vaddr_t base, size_t size)
cache_addr += min_line_size;
}

DMB(ish);
/* Ensure the cache maintenance operations complete before returning */
DSB(ish);
}
4 changes: 2 additions & 2 deletions src/arch/riscv/arch.mk
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Expand Up @@ -5,12 +5,12 @@ ARCH_SUB?=riscv64

ifeq ($(ARCH_SUB), riscv64)
CROSS_COMPILE ?= riscv64-unknown-elf-
riscv_march:=rv64imac_zicsr_zicbom
riscv_march:=rv64imac_zicsr_zicbom_zifencei
riscv_mabi:=lp64
ld_emulation:=elf64lriscv
else ifeq ($(ARCH_SUB), riscv32)
CROSS_COMPILE ?= riscv32-unknown-elf-
riscv_march:=rv32imac_zicsr_zicbom
riscv_march:=rv32imac_zicsr_zicbom_zifencei
riscv_mabi:=ilp32
ld_emulation:=elf32lriscv
else
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3 changes: 3 additions & 0 deletions src/arch/riscv/relocate.S
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Expand Up @@ -53,6 +53,9 @@ switch_space:
sub a6, a6, a4
sub a0, a0, a4

/* Synchronize instruction fetch with the data-side copy of the relocated image */
fence.i

/* Update root page table pointer */
srl a1, a1, PAGE_SHIFT
li t0, SATP_MODE_DFLT
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