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Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,7 @@ import scala.annotation.implicitNotFound
import scala.collection.mutable.HashMap
import chisel3._
import chisel3.experimental.dataview.{isView, reify, reifyIdentityView}
import chisel3.internal.firrtl.ir.{Arg, ILit, Index, LitIndex, ModuleIO, Slot, ULit}
import chisel3.internal.firrtl.ir.{Arg, ILit, Index, LitIndex, ModuleIO, OpaqueSlot, Slot, ULit}
import chisel3.internal.{throwException, Builder, ViewParent}
import chisel3.internal.binding.{AggregateViewBinding, ChildBinding, CrossModuleBinding, ViewBinding, ViewWriteability}

Expand Down Expand Up @@ -260,7 +260,8 @@ object Lookupable {
def unrollCoordinates(res: List[Arg], d: Data): (List[Arg], Data) = d.binding.get match {
case ChildBinding(parent) =>
d.getRef match {
case arg @ (_: Slot | _: Index | _: LitIndex | _: ModuleIO) => unrollCoordinates(arg :: res, parent)
case arg @ (_: Slot | _: Index | _: LitIndex | _: ModuleIO | _: OpaqueSlot) =>
unrollCoordinates(arg :: res, parent)
case other => err(s"unrollCoordinates failed for '$arg'! Unexpected arg '$other'")
}
case _ => (res, d)
Expand All @@ -274,6 +275,7 @@ object Lookupable {
case (LitIndex(_, n), vec: Vec[_]) => vec.apply(n)
case (Index(_, ILit(n)), vec: Vec[_]) => vec.apply(n.toInt)
case (ModuleIO(_, name), rec: Record) => rec._elements(name)
case (OpaqueSlot(_), rec: Record) => rec._elements("")
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Is it okay to drop OpaqueSlot's name here?

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I appreciate the close eye--OpaqueSlot's don't actually have a name (required to be ""), that's a reference to the parent Data so okay in this case!

case (arg, _) => err(s"Unexpected Arg '$arg' applied to '$d'! Root was '$start'.")
}
applyCoordinates(coor.tail, next)
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -329,6 +329,24 @@ class DefinitionSpec extends AnyFunSpec with Matchers with FileCheck {
|""".stripMargin
)
}
it("(1.o): should work on OpaqueTypes") {
class Top extends Module {
val defn = Definition(new HasOpaqueType)
mark(defn.in, "in")
mark(defn.wire, "wire")
}
ChiselStage
.emitCHIRRTL(new Top)
.fileCheck()(
"""|CHECK: "class":"chiselTests.experimental.hierarchy.Annotations$MarkAnnotation"
|CHECK-NEXT: "target":"~|HasOpaqueType>in"
|CHECK-NEXT: "tag":"in"
|CHECK: "class":"chiselTests.experimental.hierarchy.Annotations$MarkAnnotation"
|CHECK-NEXT: "target":"~|HasOpaqueType>wire"
|CHECK-NEXT: "tag":"wire"
|""".stripMargin
)
}
}
describe("(2): Annotations on designs not in the same chisel compilation") {
// Extract the built `AddTwo` module for use in other tests.
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -5,8 +5,9 @@ package chiselTests.experimental.hierarchy
import chisel3._
import chisel3.util.{SRAM, Valid}
import chisel3.experimental.hierarchy._
import chisel3.experimental.{attach, Analog, BaseModule}
import chisel3.experimental.{attach, Analog, BaseModule, OpaqueType}
import chisel3.reflect.DataMirror
import scala.collection.immutable.SeqMap

object Examples {
import Annotations._
Expand Down Expand Up @@ -424,6 +425,29 @@ object Examples {
@public val parameterized = ParameterizedUserDefinedType(List(1, 2, 3), inst1)
}

class OpaqueRecord extends Record with OpaqueType {
private val underlying = UInt(8.W)
val elements = SeqMap("" -> underlying)
}

@instantiable
class HasOpaqueType extends Module {
@public val in = IO(Input(new OpaqueRecord))
@public val out = IO(Output(new OpaqueRecord))
@public val wire = Wire(new OpaqueRecord)
wire := in
out := wire
}

class OpaqueRecordBundle extends Bundle {
val x = new OpaqueRecord
}

@instantiable
class HasFlatIOWithOpaque extends RawModule {
@public val io = FlatIO(new OpaqueRecordBundle)
}

// For test 9.c in DefinitionSpec - testing .toDefinition on Instance from imported Definition
@instantiable
class BarForImport extends RawModule {
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -331,6 +331,40 @@ class InstanceSpec extends AnyFunSpec with Matchers with Utils with FileCheck {
|""".stripMargin
)
}
it("(1.o): should work on OpaqueTypes") {
class Top extends Module {
val definition = Definition(new HasOpaqueType)
val i0 = Instance(definition)
mark(i0.in, "in")
mark(i0.wire, "wire")
}
ChiselStage
.emitCHIRRTL(new Top)
.fileCheck()(
"""|CHECK: "class":"chiselTests.experimental.hierarchy.Annotations$MarkAnnotation"
|CHECK-NEXT: "target":"~|Top/i0:HasOpaqueType>in"
|CHECK-NEXT: "tag":"in"
|CHECK: "class":"chiselTests.experimental.hierarchy.Annotations$MarkAnnotation"
|CHECK-NEXT: "target":"~|Top/i0:HasOpaqueType>wire"
|CHECK-NEXT: "tag":"wire"
|""".stripMargin
)
}
it("(1.p): should work on views (e.g. FlatIO) containing OpaqueTypes") {
class Top extends Module {
val definition = Definition(new HasFlatIOWithOpaque)
val i0 = Instance(definition)
mark(i0.io.x, "x")
}
ChiselStage
.emitCHIRRTL(new Top)
.fileCheck()(
"""|CHECK: "class":"chiselTests.experimental.hierarchy.Annotations$MarkAnnotation"
|CHECK-NEXT: "target":"~|Top/i0:HasFlatIOWithOpaque>x"
|CHECK-NEXT: "tag":"x"
|""".stripMargin
)
}
}
describe("(2) Annotations on designs not in the same chisel compilation") {
// Extract the built `AddTwo` module for use in other tests.
Expand Down
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