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We need to maintain `flushed = cfg_spm` when transitioning to Idle. Other than that, updates to `flushed` in `FsmInitFlush` are superfluous: `to_flush` tracks what to flush, `FsmEndFlush` updates `flushed`. Fixes #28, where `flushed` is wrongly updated, causing an infinite loop. Functionally equivalent to #26. Co-authored-by: Flavia Guella <flavia.guella@epfl.ch>
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Isn't there both config_pat and config_no_pat that this would need to be merged into? |
* Make simulation tests work with VCS (update dependencies, gitignore)
The current version of AXI was released in late-2025, but it has
incompatibilities that prevent it from being run in simulation
under VCS, so update it and the other dependencies to newer
versions.
Also adds temporary files generated by VCS to .gitignore.
* testbench: Reset performance counters after each sub-test
This allows you to see how each different kind of test
affects the varying event counters exposed. Useful for
future commits modifying the tests to test functionality
using the event counters.
* testbench: Space out sub-tests to make it easier to see visually
They all sort of blur together with the perf counter printing.
* testbench: use all-ones value '1 preferentially over {32{1'b1}}
This is easier to read and @phsauter also prefers it.
* testbench: Test coalesced explicit flush and SPM writes
This adds a test for the issue fixed by PR 22, where this
resulted in the cache getting stuck in bypass mode. Note
that this test is unable to identify the issue in PR 22
* testbench: Assert behaviour based on the event counters
We can utilise the event counters to make the tests able
to check behaviour of the cache; that is, whether events
are causes misses/hits in the LLC ways and thus test
configuration of SPM vs LLC has been set correctly.
…mparison Root cause: bitwise ~^ between a temporary tag_data_t struct and ram_rdata produces a flattened XNOR result. Re-slicing it back into a packed struct causes single-bit fields (val, dit) to read 0 regardless of actual values in some compilators (VCS + Simon). Fix: drop ram_compared, replace with: - tag: XNOR reduction with explicit Bist/Lookup mux on tag field - val, dit: direct == comparison against bist_pattern Affected signal: bist_res[i], which feeds axi_llc_tag_pattern_gen. Lookup/Flush behavior unchanged (tag_equ unaffected). Verified in simulation: ram_compared.val was 0 with both operands == 1.
* axi_llc: Make AXI ID lookup width configurable * test: Add AXI ID lookup width simulation matrix * test: Cover non-power-of-two ID lookup widths
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#30 Fixed a potential hang on flush. Merge it into gwaihir.