gwaihir: Track upstream fixes

.github/workflows/ci.yml

@@ -19,7 +19,7 @@ env:
 
 jobs:
   check-clean:
-    runs-on: ubuntu-latest
+    runs-on: ubuntu-22.04
     steps:
       - uses: actions/checkout@v4
       - uses: actions/setup-python@v5
@@ -40,7 +40,7 @@ jobs:
           make clean
           git status && test -z "$(git status --porcelain)"
   check-stale:
-    runs-on: ubuntu-latest
+    runs-on: ubuntu-22.04
     steps:
       - uses: actions/checkout@v4
       - uses: actions/setup-python@v5
@@ -60,7 +60,7 @@ jobs:
           make -B pickle doc graph regs
           git status && test -z "$(git status --porcelain)"
   lint:
-    runs-on: ubuntu-latest
+    runs-on: ubuntu-22.04
     needs: [check-clean, check-stale]
     strategy:
       fail-fast: false
@@ -83,7 +83,7 @@ jobs:
         if: ${{ matrix.lint_check == 'python' }}
         run: scripts/python-lint
   lint-commit:
-    runs-on: ubuntu-latest
+    runs-on: ubuntu-22.04
     needs: [check-clean, check-stale]
     steps:
       - uses: actions/checkout@v4
@@ -117,7 +117,7 @@ jobs:
   #         reviewdog_reporter: github-check
 
   analyze-contributors:
-    runs-on: ubuntu-latest
+    runs-on: ubuntu-22.04
     needs: lint
     steps:
       - uses: actions/checkout@v4
@@ -130,7 +130,7 @@ jobs:
           path: contributions.txt
           retention-days: 7
   analyze-todos:
-    runs-on: ubuntu-latest
+    runs-on: ubuntu-22.04
     needs: lint
     continue-on-error: true
     steps:

.gitignore

@@ -14,3 +14,8 @@ pickle
 doc/morty*
 bender
 morty*
+
+ucli.key
+vc_hdrs.h
+work-vcs/
+lmgrd.daidir/

Bender.lock

@@ -7,31 +7,31 @@ packages:
     dependencies:
     - common_cells
   axi:
-    revision: 587355b77b8ce94dcd600efbd5d5bd118ff913a7
-    version: 0.39.4
+    revision: a8c53cee2520d328d390c507c88818e8ac144c8c
+    version: 0.39.10
     source:
       Git: https://github.com/pulp-platform/axi.git
     dependencies:
     - common_cells
     - common_verification
     - tech_cells_generic
   common_cells:
-    revision: c27bce39ebb2e6bae52f60960814a2afca7bd4cb
-    version: 1.37.0
+    revision: 9ca8a7655f741e7dd5736669a20a301325194c28
+    version: 1.39.0
     source:
       Git: https://github.com/pulp-platform/common_cells.git
     dependencies:
     - common_verification
     - tech_cells_generic
   common_verification:
-    revision: 9c07fa860593b2caabd9b5681740c25fac04b878
-    version: 0.2.3
+    revision: fb1885f48ea46164a10568aeff51884389f67ae3
+    version: 0.2.5
     source:
       Git: https://github.com/pulp-platform/common_verification.git
     dependencies: []
   register_interface:
-    revision: ae616e5a1ec2b41e72d200e5ab09c65e94aebd3d
-    version: 0.4.4
+    revision: d6e1d4cdaab7870f4faf3f88a1c788eaf5ac129d
+    version: 0.4.7
     source:
       Git: https://github.com/pulp-platform/register_interface.git
     dependencies:

Bender.yml

@@ -9,7 +9,7 @@ package:
     - "Wolfgang Roenninger <wroennin@ethz.ch>"
 
 dependencies:
-  axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.4 }
+  axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.10 }
   common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 }
   common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.0 }
   register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.4 }

Makefile

@@ -6,6 +6,7 @@
 
 BENDER ?= bender
 PYTHON ?= python3
+VSIM   ?= vsim
 
 REGGEN_PATH  = $(shell $(BENDER) path register_interface)/vendor/lowrisc_opentitan/util/regtool.py
 REGGEN	     = $(PYTHON) $(REGGEN_PATH)
@@ -30,6 +31,7 @@ help:
 	@echo "-------------"
 	@echo ""
 	@echo "bin/axi_llc.vcs:                   creates the VCS executable"
+	@echo "sim_id_widths:                     simulates representative AXI ID lookup widths"
 	@echo "pickle:                            uses morty to generate a pickled version of the hardware"
 	@echo "doc:                               generates the documentation in doc/morty"
 	@echo "graph:                             generates the module hierarchy graph in doc/morty-graph"
@@ -52,7 +54,7 @@ regs:
 # QuestaSim
 # --------------
 
-.PHONY: sim_clean
+.PHONY: sim_id_widths sim_clean
 
 VLOG_ARGS += -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale \"1 ns / 1 ps\"
 
@@ -65,6 +67,9 @@ endef
 scripts/compile_vsim.tcl: Bender.yml
 	$(call generate_vsim, $@, -t rtl -t test,..)
 
+sim_id_widths: scripts/compile_vsim.tcl
+	$(VSIM) -c -do "source scripts/compile_vsim.tcl; source scripts/test_id_widths_vsim.tcl"
+
 sim_clean:
 	rm -rf scripts/compile_vsim.tcl
 	rm -rf work

scripts/start_vcs

@@ -3,4 +3,4 @@
 # Solderpad Hardware License, Version 0.51, see LICENSE for details.
 # SPDX-License-Identifier: SHL-0.51
 
-bin/axi_llc.vcs +vcs+lic+wait | tee logs/axi_llc.vcs.log
+bin/axi_llc.vcs +vcs+lic+wait +ntb_random_seed=1 | tee logs/axi_llc.vcs.log

scripts/start_vsim.tcl

@@ -4,7 +4,7 @@
 
 # Author: Thomas Benz <tbenz@iis.ee.ethz.ch>
 
-vsim -t 1ps -voptargs=+acc tb_axi_llc -logfile logs/axi_llc.vsim.log -wlf logs/axi_llc.wlf
+vsim -t 1ps -voptargs=+acc -sv_seed 1 tb_axi_llc -logfile logs/axi_llc.vsim.log -wlf logs/axi_llc.wlf
 
 set StdArithNoWarnings 1
 set NumericStdNoWarnings 1

scripts/test_id_widths_vsim.tcl

@@ -0,0 +1,50 @@
+# Copyright 2026 ETH Zurich and University of Bologna.
+# Solderpad Hardware License, Version 0.51, see LICENSE for details.
+# SPDX-License-Identifier: SHL-0.51
+#
+# Author: Philippe Sauter <phsauter@iis.ee.ethz.ch>
+
+set regression_failed 0
+
+proc run_id_width_test {name id_width lookup_bits} {
+  global regression_failed
+
+  puts "================================================================"
+  puts "= Running AXI ID configuration: width=$id_width lookup=$lookup_bits"
+  puts "================================================================"
+
+  set transcript_name "logs/axi_llc.id_width_${name}.vsim.log"
+  file delete -force $transcript_name
+  transcript file $transcript_name
+
+  vsim -t 1ps -voptargs=+acc -sv_seed 1 \
+      -GTbAxiIdWidthFull=$id_width \
+      -GTbAxiIdLookupBits=$lookup_bits \
+      -wlf "logs/axi_llc.id_width_${name}.wlf" \
+      tb_axi_llc
+
+  onfinish stop
+  set StdArithNoWarnings 1
+  set NumericStdNoWarnings 1
+  run 100 us
+  quit -sim
+
+  transcript file {}
+  set transcript_fd [open $transcript_name r]
+  set transcript_data [read $transcript_fd]
+  close $transcript_fd
+  if {[regexp -line {^# \*\* (Error|Fatal)( \([^)]*\))?:} $transcript_data]} {
+    puts "Regression errors detected in $transcript_name"
+    set regression_failed 1
+  }
+}
+
+run_id_width_test width1_lookup1 1 1
+run_id_width_test width2_lookup1 2 1
+run_id_width_test width3_lookup3 3 3
+run_id_width_test width5_lookup3 5 3
+run_id_width_test width6_lookup2 6 2
+run_id_width_test width6_lookup4 6 4
+run_id_width_test width6_lookup5 6 5
+
+quit -code $regression_failed -f

src/axi_llc_config.sv

@@ -448,16 +448,16 @@ module axi_llc_config #(
         // this state determines which cache way should be flushed
         // it also sets up the counters for state-keeping how far
         // the flush operation has progressed
-        // define if the user requested a flush
         to_flush_d = (conf_regs_i.cfg_flush | conf_regs_i.cfg_spm) & ~conf_regs_i.flushed;
-        conf_regs_o.flushed     = conf_regs_i.cfg_spm & conf_regs_i.flushed;
-        conf_regs_o.flushed_en  = 1'b1;
         // now determine if we have something to do at all
         if (to_flush_d == '0) begin
           // nothing to flush, go to idle
           flush_state_d = FsmIdle;
           // clear the cfg_flush register.
           conf_regs_o.cfg_flush = set_asso_t'(1'b0);
+          // reset the flushed register to SPM.
+          conf_regs_o.flushed     = conf_regs_i.cfg_spm;
+          conf_regs_o.flushed_en  = 1'b1;
         end else begin
           flush_state_d = FsmSendFlush;
           load_cnt      = 1'b1;

src/axi_llc_hit_miss.sv

@@ -48,7 +48,9 @@ module axi_llc_hit_miss #(
   /// Way indicator, is a onehot signal with width: `Cfg.SetAssociativity`.
   parameter type                       way_ind_t = logic,
   /// Whether to print SRAM configs
-  parameter bit                        PrintSramCfg = 0
+  parameter bit                        PrintSramCfg = 0,
+  /// Number of low AXI ID bits used for miss counters.
+  parameter int unsigned               AxiIdLookupBits = 32'd0
 ) (
   /// Clock, positive edge triggered.
   input  logic     clk_i,
@@ -360,8 +362,9 @@ module axi_llc_hit_miss #(
   assign cnt_up.valid = ~desc_o.flush & miss_valid_o & miss_ready_i;
 
   axi_llc_miss_counters #(
-    .Cfg     ( Cfg    ),
-    .cnt_t   ( cnt_t  )
+    .Cfg             ( Cfg             ),
+    .AxiIdLookupBits ( AxiIdLookupBits ),
+    .cnt_t           ( cnt_t           )
   ) i_miss_counters (
     .clk_i      (      clk_i ),
     .rst_ni     (     rst_ni ),

src/axi_llc_pkg.sv

@@ -229,11 +229,6 @@ package axi_llc_pkg;
   parameter int unsigned MissCntWidth     = 32'd5;
   /// Writes are counted separately. Writes have to be in order, only one counter.
   parameter int unsigned MissCntMaxWWidth = 32'd7;
-  /// This number tells us how many bits of the slave port AXI ID are used for pointing on a counter
-  /// * Translates in 2**`UseIdBits` counters inferred.
-  /// * Set this parameter to the slave port AXI ID width if you want one counter for each AXI ID.
-  parameter int unsigned UseIdBits        = 32'd4;
-
   /// This adds a spill register in the response path of the tag stroage unit.
   /// This should be used to achieve good timing characteristics in synthsis as the longest
   /// path in the design comes out of the tag storage macros.

src/axi_llc_reg_wrap.sv

@@ -189,7 +189,11 @@ module axi_llc_reg_wrap #(
   parameter type axi_addr_t     = logic[AxiAddrWidth-1:0],
   /// Dependent parameter, do **not** overwrite!
   /// Data type of set associativity wide registers
-  parameter type way_ind_t      = logic[SetAssociativity-1:0]
+  parameter type way_ind_t      = logic[SetAssociativity-1:0],
+  /// Number of low AXI ID bits used for demux tracking and miss counters.
+  /// The number of inferred bookkeeping entries grows exponentially with this value.
+  parameter int unsigned AxiIdLookupBits =
+      (AxiIdWidth < 32'd4) ? AxiIdWidth : 32'd4
 ) (
   /// Rising-edge clock of all ports.
   input logic clk_i,
@@ -264,6 +268,7 @@ module axi_llc_reg_wrap #(
     .NumLines         ( NumLines              ),
     .NumBlocks        ( NumBlocks             ),
     .AxiIdWidth       ( AxiIdWidth            ),
+    .AxiIdLookupBits  ( AxiIdLookupBits       ),
     .AxiAddrWidth     ( AxiAddrWidth          ),
     .AxiDataWidth     ( AxiDataWidth          ),
     .AxiUserWidth     ( AxiUserWidth          ),

src/axi_llc_top.sv

@@ -5,6 +5,8 @@
 // Author: Wolfgang Roenninger <wroennin@iis.ee.ethz.ch>
 // Date:   30.04.2019
 
+`include "common_cells/assertions.svh"
+
 /// Contains the top_level of the axi_llc with structs as AXI connections.
 /// The standard configuration is a cache size of 512KByte with a set-associativity
 /// of 8, and line length of 8 blocks, one block equals the AXI data width of the
@@ -187,7 +189,11 @@ module axi_llc_top #(
   parameter type axi_addr_t     = logic[AxiAddrWidth-1:0],
   /// Dependent parameter, do **not** overwrite!
   /// Data type of set associativity wide registers
-  parameter type way_ind_t      = logic[SetAssociativity-1:0]
+  parameter type way_ind_t      = logic[SetAssociativity-1:0],
+  /// Number of low AXI ID bits used for demux tracking and miss counters.
+  /// The number of inferred bookkeeping entries grows exponentially with this value.
+  parameter int unsigned AxiIdLookupBits =
+      (AxiIdWidth < 32'd4) ? AxiIdWidth : 32'd4
 ) (
   /// Rising-edge clock of all ports.
   input logic clk_i,
@@ -470,7 +476,7 @@ module axi_llc_top #(
     .axi_resp_t     ( slv_resp_t             ),
     .NoMstPorts     ( 32'd2                  ),
     .MaxTrans       ( axi_llc_pkg::MaxTrans  ),
-    .AxiLookBits    ( axi_llc_pkg::UseIdBits ),
+    .AxiLookBits    ( AxiIdLookupBits         ),
     .SpillAw        ( 1'b0                   ),
     .SpillW         ( 1'b0                   ),
     .SpillB         ( 1'b0                   ),
@@ -567,13 +573,14 @@ module axi_llc_top #(
   );
 
   axi_llc_hit_miss #(
-    .Cfg          ( Cfg          ),
-    .AxiCfg       ( AxiCfg       ),
-    .desc_t       ( llc_desc_t   ),
-    .lock_t       ( lock_t       ),
-    .cnt_t        ( cnt_t        ),
-    .way_ind_t    ( way_ind_t    ),
-    .PrintSramCfg ( PrintSramCfg )
+    .Cfg             ( Cfg             ),
+    .AxiCfg          ( AxiCfg          ),
+    .AxiIdLookupBits ( AxiIdLookupBits ),
+    .desc_t          ( llc_desc_t      ),
+    .lock_t          ( lock_t          ),
+    .cnt_t           ( cnt_t           ),
+    .way_ind_t       ( way_ind_t       ),
+    .PrintSramCfg    ( PrintSramCfg    )
   ) i_hit_miss_unit (
     .clk_i,
     .rst_ni,
@@ -933,6 +940,11 @@ module axi_llc_top #(
     default: '0
   };
 
+  `ASSERT_INIT(AxiIdLookupBitsNonZero, AxiIdLookupBits > 32'd0,
+      "AxiIdLookupBits must be greater than zero.")
+  `ASSERT_INIT(AxiIdLookupBitsValid, AxiIdLookupBits <= AxiIdWidth,
+      "AxiIdLookupBits must not exceed AxiIdWidth.")
+
 // pragma translate_off
 `ifndef VERILATOR
   initial begin : proc_assert_axi_params
@@ -941,7 +953,7 @@ module axi_llc_top #(
     axi_id_width   : assert(AxiIdWidth > 32'd0) else
       $fatal(1, "Parameter `AxiIdWidth` has to be > 0!");
     axi_data_width : assert(AxiDataWidth inside {32'd8, 32'd16, 32'd32, 32'd64,
-                                                 32'd128, 32'd256, 32'd512, 32'd1028}) else
+                                                 32'd128, 32'd256, 32'd512, 32'd1024}) else
       $fatal(1, "Parameter `AxiDataWidth` has to be inside the AXI4+ATOP specification!");
     axi_user_width : assert(AxiUserWidth > 32'd0) else
       $fatal(1, "Parameter `AxiUserWidth` has to be > 0!");